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Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interru
From: |
Serge Vakulenko |
Subject: |
Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode. |
Date: |
Sun, 5 Jul 2015 20:31:50 -0700 |
On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
<address@hidden> wrote:
> On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno <address@hidden> wrote:
>> On 2015-06-30 21:12, Serge Vakulenko wrote:
>>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
>>> index c476166..ab830ee 100644
>>> --- a/target-mips/cpu.h
>>> +++ b/target-mips/cpu.h
>>> @@ -664,7 +669,9 @@ static inline int
>>> cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
>>> if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
>>> /* A MIPS configured with a vectorizing external interrupt
>>> controller
>>> will feed a vector into the Cause pending lines. The core treats
>>> - the status lines as a vector level, not as indiviual masks. */
>>> + the status lines as a vector level, not as individual masks. */
>>> + pending >>= CP0Ca_IP + 2;
>>> + status >>= CP0Ca_IP + 2;
>>> r = pending > status;
>>
>> I don't think it's needed. As the pending and status field have been
>> masked above, we don't need to shift them to do the comparison.
This is not true. The values still need to be shifted to get rid of
soft interrupt bits, otherwise the comparison becomes incorrect.
Best wishes,
--Serge
>> --
>> Aurelien Jarno GPG: 4096R/1DDD8C9B
>> address@hidden http://www.aurel32.net
- Re: [Qemu-devel] [PATCH pic32 v2 2/5] Fixed random index generation for TLBWR instruction. It was not quite random and did not skip Wired entries., (continued)
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Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode., Aurelien Jarno, 2015/07/06
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Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP., Serge Vakulenko, 2015/07/05
Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP., Aurelien Jarno, 2015/07/06
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