Re: [Qemu-devel] [PATCH v5 05/11] target-i386: exception handling for FPU instructions

[Aurelien Jarno]

On 2015-07-06 11:26, Pavel Dovgalyuk wrote:
> This patch fixes exception handling for FPU instructions.
> 
> Signed-off-by: Pavel Dovgalyuk <address@hidden>
> ---
>  target-i386/fpu_helper.c |  146 
> +++++++++++++++++++++++++---------------------
>  1 files changed, 80 insertions(+), 66 deletions(-)
> 
> diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
> index 30d34d5..360f228 100644
> --- a/target-i386/fpu_helper.c
> +++ b/target-i386/fpu_helper.c
> @@ -68,22 +68,24 @@ static inline void fpop(CPUX86State *env)
>      env->fpstt = (env->fpstt + 1) & 7;
>  }
>  
> -static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
> +static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr,
> +                                   uintptr_t retaddr)
>  {
>      CPU_LDoubleU temp;
>  
> -    temp.l.lower = cpu_ldq_data(env, ptr);
> -    temp.l.upper = cpu_lduw_data(env, ptr + 8);
> +    temp.l.lower = cpu_ldq_data_ra(env, ptr, retaddr);
> +    temp.l.upper = cpu_lduw_data_ra(env, ptr + 8, retaddr);
>      return temp.d;
>  }
>  
> -static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong 
> ptr)
> +static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong 
> ptr,
> +                               uintptr_t retaddr)Status
>  {
>      CPU_LDoubleU temp;
>  
>      temp.d = f;
> -    cpu_stq_data(env, ptr, temp.l.lower);
> -    cpu_stw_data(env, ptr + 8, temp.l.upper);
> +    cpu_stq_data_ra(env, ptr, temp.l.lower, retaddr);
> +    cpu_stw_data_ra(env, ptr + 8, temp.l.upper, retaddr);
>  }
>  
>  /* x87 FPU helpers */
> @@ -126,10 +128,10 @@ static inline floatx80 helper_fdiv(CPUX86State *env, 
> floatx80 a, floatx80 b)
>      return floatx80_div(a, b, &env->fp_status);
>  }
>  
> -static void fpu_raise_exception(CPUX86State *env)
> +static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
>  {
>      if (env->cr[0] & CR0_NE_MASK) {
> -        raise_exception(env, EXCP10_COPR);
> +        raise_exception_ra(env, EXCP10_COPR, retaddr);
>      }
>  #if !defined(CONFIG_USER_ONLY)
>      else {
> @@ -314,14 +316,14 @@ void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
>      int new_fpstt;
>  
>      new_fpstt = (env->fpstt - 1) & 7;
> -    env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
> +    env->fpregs[new_fpstt].d = helper_fldt(env, ptr, GETPC());
>      env->fpstt = new_fpstt;
>      env->fptags[new_fpstt] = 0; /* validate stack entry */
>  }
>  
>  void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
>  {
> -    helper_fstt(env, ST0, ptr);
> +    helper_fstt(env, ST0, ptr, GETPC());
>  }
>  
>  void helper_fpush(CPUX86State *env)
> @@ -604,7 +606,7 @@ void helper_fclex(CPUX86State *env)
>  void helper_fwait(CPUX86State *env)
>  {
>      if (env->fpus & FPUS_SE) {
> -        fpu_raise_exception(env);
> +        fpu_raise_exception(env, GETPC());
>      }
>  }
>  
> @@ -634,11 +636,11 @@ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
>  
>      val = 0;
>      for (i = 8; i >= 0; i--) {
> -        v = cpu_ldub_data(env, ptr + i);
> +        v = cpu_ldub_data_ra(env, ptr + i, GETPC());
>          val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
>      }
>      tmp = int64_to_floatx80(val, &env->fp_status);
> -    if (cpu_ldub_data(env, ptr + 9) & 0x80) {
> +    if (cpu_ldub_data_ra(env, ptr + 9, GETPC()) & 0x80) {
>          tmp = floatx80_chs(tmp);
>      }
>      fpush(env);
> @@ -655,10 +657,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
>      mem_ref = ptr;
>      mem_end = mem_ref + 9;
>      if (val < 0) {
> -        cpu_stb_data(env, mem_end, 0x80);
> +        cpu_stb_data_ra(env, mem_end, 0x80, GETPC());
>          val = -val;
>      } else {
> -        cpu_stb_data(env, mem_end, 0x00);
> +        cpu_stb_data_ra(env, mem_end, 0x00, GETPC());
>      }
>      while (mem_ref < mem_end) {
>          if (val == 0) {
> @@ -667,10 +669,10 @@ void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
>          v = val % 100;
>          val = val / 100;
>          v = ((v / 10) << 4) | (v % 10);
> -        cpu_stb_data(env, mem_ref++, v);
> +        cpu_stb_data_ra(env, mem_ref++, v, GETPC());
>      }
>      while (mem_ref < mem_end) {
> -        cpu_stb_data(env, mem_ref++, 0);
> +        cpu_stb_data_ra(env, mem_ref++, 0, GETPC());
>      }
>  }
>  
> @@ -978,7 +980,8 @@ void helper_fxam_ST0(CPUX86State *env)
>      }
>  }
>  
> -void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
> +static void do_fstenv(CPUX86State *env, target_ulong ptr, int data32,
> +                      uintptr_t retaddr)
>  {
>      int fpus, fptag, exp, i;
>      uint64_t mant;
> @@ -1006,37 +1009,43 @@ void helper_fstenv(CPUX86State *env, target_ulong 
> ptr, int data32)
>      }
>      if (data32) {
>          /* 32 bit */
> -        cpu_stl_data(env, ptr, env->fpuc);
> -        cpu_stl_data(env, ptr + 4, fpus);
> -        cpu_stl_data(env, ptr + 8, fptag);
> -        cpu_stl_data(env, ptr + 12, 0); /* fpip */
> -        cpu_stl_data(env, ptr + 16, 0); /* fpcs */
> -        cpu_stl_data(env, ptr + 20, 0); /* fpoo */
> -        cpu_stl_data(env, ptr + 24, 0); /* fpos */
> +        cpu_stl_data_ra(env, ptr, env->fpuc, retaddr);
> +        cpu_stl_data_ra(env, ptr + 4, fpus, retaddr);
> +        cpu_stl_data_ra(env, ptr + 8, fptag, retaddr);
> +        cpu_stl_data_ra(env, ptr + 12, 0, retaddr); /* fpip */
> +        cpu_stl_data_ra(env, ptr + 16, 0, retaddr); /* fpcs */
> +        cpu_stl_data_ra(env, ptr + 20, 0, retaddr); /* fpoo */
> +        cpu_stl_data_ra(env, ptr + 24, 0, retaddr); /* fpos */
>      } else {
>          /* 16 bit */
> -        cpu_stw_data(env, ptr, env->fpuc);
> -        cpu_stw_data(env, ptr + 2, fpus);
> -        cpu_stw_data(env, ptr + 4, fptag);
> -        cpu_stw_data(env, ptr + 6, 0);
> -        cpu_stw_data(env, ptr + 8, 0);
> -        cpu_stw_data(env, ptr + 10, 0);
> -        cpu_stw_data(env, ptr + 12, 0);
> +        cpu_stw_data_ra(env, ptr, env->fpuc, retaddr);
> +        cpu_stw_data_ra(env, ptr + 2, fpus, retaddr);
> +        cpu_stw_data_ra(env, ptr + 4, fptag, retaddr);
> +        cpu_stw_data_ra(env, ptr + 6, 0, retaddr);
> +        cpu_stw_data_ra(env, ptr + 8, 0, retaddr);
> +        cpu_stw_data_ra(env, ptr + 10, 0, retaddr);
> +        cpu_stw_data_ra(env, ptr + 12, 0, retaddr);
>      }
>  }
>  
> -void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
> +void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
> +{
> +    do_fstenv(env, ptr, data32, GETPC());
> +}
> +
> +static void do_fldenv(CPUX86State *env, target_ulong ptr, int data32,
> +                      uintptr_t retaddr)
>  {
>      int i, fpus, fptag;
>  
>      if (data32) {
> -        cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
> -        fpus = cpu_lduw_data(env, ptr + 4);
> -        fptag = cpu_lduw_data(env, ptr + 8);
> +        cpu_set_fpuc(env, cpu_lduw_data_ra(env, ptr, retaddr));
> +        fpus = cpu_lduw_data_ra(env, ptr + 4, retaddr);
> +        fptag = cpu_lduw_data_ra(env, ptr + 8, retaddr);
>      } else {
> -        cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
> -        fpus = cpu_lduw_data(env, ptr + 2);
> -        fptag = cpu_lduw_data(env, ptr + 4);
> +        cpu_set_fpuc(env, cpu_lduw_data_ra(env, ptr, retaddr));
> +        fpus = cpu_lduw_data_ra(env, ptr + 2, retaddr);
> +        fptag = cpu_lduw_data_ra(env, ptr + 4, retaddr);
>      }
>      env->fpstt = (fpus >> 11) & 7;
>      env->fpus = fpus & ~0x3800;
> @@ -1046,17 +1055,22 @@ void helper_fldenv(CPUX86State *env, target_ulong 
> ptr, int data32)
>      }
>  }
>  
> +void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
> +{
> +    do_fldenv(env, ptr, data32, GETPC());
> +}
> +
>  void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
>  {
>      floatx80 tmp;
>      int i;
>  
> -    helper_fstenv(env, ptr, data32);
> +    do_fstenv(env, ptr, data32, GETPC());
>  
>      ptr += (14 << data32);
>      for (i = 0; i < 8; i++) {
>          tmp = ST(i);
> -        helper_fstt(env, tmp, ptr);
> +        helper_fstt(env, tmp, ptr, GETPC());
>          ptr += 10;
>      }
>  
> @@ -1079,11 +1093,11 @@ void helper_frstor(CPUX86State *env, target_ulong 
> ptr, int data32)
>      floatx80 tmp;
>      int i;
>  
> -    helper_fldenv(env, ptr, data32);
> +    do_fldenv(env, ptr, data32, GETPC());
>      ptr += (14 << data32);
>  
>      for (i = 0; i < 8; i++) {
> -        tmp = helper_fldt(env, ptr);
> +        tmp = helper_fldt(env, ptr, GETPC());
>          ST(i) = tmp;
>          ptr += 10;
>      }
> @@ -1109,7 +1123,7 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, 
> int data64)
>  
>      /* The operand must be 16 byte aligned */
>      if (ptr & 0xf) {
> -        raise_exception(env, EXCP0D_GPF);
> +        raise_exception_ra(env, EXCP0D_GPF, GETPC());
>      }
>  
>      fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
> @@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong 
> ptr, int data64)
>      for (i = 0; i < 8; i++) {
>          fptag |= (env->fptags[i] << i);
>      }
> -    cpu_stw_data(env, ptr, env->fpuc);
> -    cpu_stw_data(env, ptr + 2, fpus);
> -    cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
> +    cpu_stw_data_ra(env, ptr, env->fpuc, GETPC());
> +    cpu_stw_data_ra(env, ptr + 2, fpus, GETPC());
> +    cpu_stw_data_ra(env, ptr + 4, fptag ^ 0xff, GETPC());
>  #ifdef TARGET_X86_64
>      if (data64) {
> -        cpu_stq_data(env, ptr + 0x08, 0); /* rip */
> -        cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
> +        cpu_stq_data_ra(env, ptr + 0x08, 0, GETPC()); /* rip */
> +        cpu_stq_data_ra(env, ptr + 0x10, 0, GETPC()); /* rdp */
>      } else
>  #endif
>      {
> -        cpu_stl_data(env, ptr + 0x08, 0); /* eip */
> -        cpu_stl_data(env, ptr + 0x0c, 0); /* sel  */
> -        cpu_stl_data(env, ptr + 0x10, 0); /* dp */
> -        cpu_stl_data(env, ptr + 0x14, 0); /* sel  */
> +        cpu_stl_data_ra(env, ptr + 0x08, 0, GETPC()); /* eip */
> +        cpu_stl_data_ra(env, ptr + 0x0c, 0, GETPC()); /* sel  */
> +        cpu_stl_data_ra(env, ptr + 0x10, 0, GETPC()); /* dp */
> +        cpu_stl_data_ra(env, ptr + 0x14, 0, GETPC()); /* sel  */
>      }
>  
>      addr = ptr + 0x20;
>      for (i = 0; i < 8; i++) {
>          tmp = ST(i);
> -        helper_fstt(env, tmp, addr);
> +        helper_fstt(env, tmp, addr, GETPC());
>          addr += 16;
>      }
>  
>      if (env->cr[4] & CR4_OSFXSR_MASK) {
>          /* XXX: finish it */
> -        cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
> -        cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
> +        cpu_stl_data_ra(env, ptr + 0x18, env->mxcsr, GETPC()); /* mxcsr */
> +        cpu_stl_data_ra(env, ptr + 0x1c, 0x0000ffff, GETPC()); /* mxcsr_mask 
> */
>          if (env->hflags & HF_CS64_MASK) {
>              nb_xmm_regs = 16;
>          } else {
> @@ -1155,8 +1169,8 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr, 
> int data64)
>              || (env->hflags & HF_CPL_MASK)
>              || !(env->hflags & HF_LMA_MASK)) {
>              for (i = 0; i < nb_xmm_regs; i++) {
> -                cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
> -                cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
> +                cpu_stq_data_ra(env, addr, env->xmm_regs[i].XMM_Q(0), 
> GETPC());
> +                cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].XMM_Q(1), 
> GETPC());
>                  addr += 16;
>              }
>          }
> @@ -1171,12 +1185,12 @@ void helper_fxrstor(CPUX86State *env, target_ulong 
> ptr, int data64)
>  
>      /* The operand must be 16 byte aligned */
>      if (ptr & 0xf) {
> -        raise_exception(env, EXCP0D_GPF);
> +        raise_exception_ra(env, EXCP0D_GPF, GETPC());
>      }
>  
> -    cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
> -    fpus = cpu_lduw_data(env, ptr + 2);
> -    fptag = cpu_lduw_data(env, ptr + 4);
> +    cpu_set_fpuc(env, cpu_lduw_data_ra(env, ptr, GETPC()));
> +    fpus = cpu_lduw_data_ra(env, ptr + 2, GETPC());
> +    fptag = cpu_lduw_data_ra(env, ptr + 4, GETPC());
>      env->fpstt = (fpus >> 11) & 7;
>      env->fpus = fpus & ~0x3800;
>      fptag ^= 0xff;
> @@ -1186,14 +1200,14 @@ void helper_fxrstor(CPUX86State *env, target_ulong 
> ptr, int data64)
>  
>      addr = ptr + 0x20;
>      for (i = 0; i < 8; i++) {
> -        tmp = helper_fldt(env, addr);
> +        tmp = helper_fldt(env, addr, GETPC());
>          ST(i) = tmp;
>          addr += 16;
>      }
>  
>      if (env->cr[4] & CR4_OSFXSR_MASK) {
>          /* XXX: finish it */
> -        cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
> +        cpu_set_mxcsr(env, cpu_ldl_data_ra(env, ptr + 0x18, GETPC()));
>          /* cpu_ldl_data(env, ptr + 0x1c); */

Please also convert this one, even if commented out. That said:

Reviewed-by: Aurelien Jarno <address@hidden>

Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net