Re: [Qemu-devel] [RFC PATCH V6 16/18] arm: use tlb_flush*_all

[Alex Bennée]

address@hidden writes:

> From: KONRAD Frederic <address@hidden>
>
> This just use the new mechanism to ensure that each VCPU thread flush its own
> VCPU.
>
> Signed-off-by: KONRAD Frederic <address@hidden>
> ---
>  target-arm/helper.c | 45 +++++++--------------------------------------
>  1 file changed, 7 insertions(+), 38 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index ad3d5da..1995439 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -411,41 +411,25 @@ static void tlbimvaa_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                               uint64_t value)
>  {
> -    CPUState *other_cs;
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush(other_cs, 1);
> -    }
> +    tlb_flush_all(1);
>  }
>  
>  static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                               uint64_t value)
>  {
> -    CPUState *other_cs;
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush(other_cs, value == 0);
> -    }
> +    tlb_flush_all(value == 0);
>  }
>  
>  static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                               uint64_t value)
>  {
> -    CPUState *other_cs;
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
> -    }
> +    tlb_flush_page_all(value & TARGET_PAGE_MASK);
>  }
>  
>  static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                               uint64_t value)
>  {
> -    CPUState *other_cs;
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
> -    }
> +    tlb_flush_page_all(value & TARGET_PAGE_MASK);
>  }
>  
>  static const ARMCPRegInfo cp_reginfo[] = {
> @@ -2281,34 +2265,19 @@ static void tlbi_aa64_asid_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                                    uint64_t value)
>  {
> -    CPUState *other_cs;
> -    uint64_t pageaddr = sextract64(value << 12, 0, 56);
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush_page(other_cs, pageaddr);
> -    }
> +    tlb_flush_page_all(sextract64(value << 12, 0, 56));
>  }

Personally I'd keep the:

uint64_t pageaddr = sextract64(value << 12, 0, 56);

The compiler will optimise away but the reader will now what those bits
are.

>  
>  static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                                    uint64_t value)
>  {
> -    CPUState *other_cs;
> -    uint64_t pageaddr = sextract64(value << 12, 0, 56);
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush_page(other_cs, pageaddr);
> -    }
> +    tlb_flush_page_all(sextract64(value << 12, 0, 56));
>  }

ditto

>  
>  static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                                    uint64_t value)
>  {
> -    CPUState *other_cs;
> -    int asid = extract64(value, 48, 16);
> -
> -    CPU_FOREACH(other_cs) {
> -        tlb_flush(other_cs, asid == 0);
> -    }
> +    tlb_flush_all(extract64(value, 48, 16) == 0);
>  }

ditto

>  
>  static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo 
> *ri)

-- 
Alex Bennée