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[Qemu-devel] [PATCH 06/14] target-i386: Perform set/reset_inhibit_irq in
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 06/14] target-i386: Perform set/reset_inhibit_irq inline |
Date: |
Thu, 9 Jul 2015 09:17:21 +0100 |
With helpers that can be reused for other things.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/cc_helper.c | 10 ----------
target-i386/helper.h | 2 --
target-i386/translate.c | 37 ++++++++++++++++++++++++++++---------
3 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index ecbf0ec..1bf89aa 100644
--- a/target-i386/cc_helper.c
+++ b/target-i386/cc_helper.c
@@ -382,13 +382,3 @@ void helper_sti_vm(CPUX86State *env)
}
}
#endif
-
-void helper_set_inhibit_irq(CPUX86State *env)
-{
- env->hflags |= HF_INHIBIT_IRQ_MASK;
-}
-
-void helper_reset_inhibit_irq(CPUX86State *env)
-{
- env->hflags &= ~HF_INHIBIT_IRQ_MASK;
-}
diff --git a/target-i386/helper.h b/target-i386/helper.h
index e6df35c..0c957bf 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -61,8 +61,6 @@ DEF_HELPER_1(cli, void, env)
DEF_HELPER_1(sti, void, env)
DEF_HELPER_1(clac, void, env)
DEF_HELPER_1(stac, void, env)
-DEF_HELPER_1(set_inhibit_irq, void, env)
-DEF_HELPER_1(reset_inhibit_irq, void, env)
DEF_HELPER_3(boundw, void, env, tl, int)
DEF_HELPER_3(boundl, void, env, tl, int)
DEF_HELPER_1(rsm, void, env)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index eb30401..9303dc0 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2393,14 +2393,36 @@ static void gen_debug(DisasContext *s, target_ulong
cur_eip)
s->is_jmp = DISAS_TB_JUMP;
}
+static void gen_set_hflag(DisasContext *s, uint32_t mask)
+{
+ if ((s->flags & mask) == 0) {
+ TCGv_i32 t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_ori_i32(t, t, mask);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_temp_free_i32(t);
+ s->flags |= mask;
+ }
+}
+
+static void gen_reset_hflag(DisasContext *s, uint32_t mask)
+{
+ if (s->flags & mask) {
+ TCGv_i32 t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_andi_i32(t, t, ~mask);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_temp_free_i32(t);
+ s->flags &= ~mask;
+ }
+}
+
/* generate a generic end of block. Trace exception is also generated
if needed */
static void gen_eob(DisasContext *s)
{
gen_update_cc_op(s);
- if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
- gen_helper_reset_inhibit_irq(cpu_env);
- }
+ gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);
if (s->tb->flags & HF_RF_MASK) {
gen_helper_reset_rf(cpu_env);
}
@@ -5190,8 +5212,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
s->tf = 0;
}
if (s->is_jmp) {
@@ -5258,8 +5279,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* if reg == SS, inhibit interrupts/trace */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
s->tf = 0;
}
if (s->is_jmp) {
@@ -6813,8 +6833,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* interruptions are enabled only the first insn after sti */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
/* give a chance to handle pending irqs */
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
--
2.4.3
- [Qemu-devel] [PATCH 02/14] target-i386: Rearrange processing of 0F 01, (continued)
- [Qemu-devel] [PATCH 02/14] target-i386: Rearrange processing of 0F 01, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 03/14] target-i386: Add XSAVE extension, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 04/14] target-i386: Implement XSAVEOPT, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 05/14] target-i386: Enable control registers for MPX, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 06/14] target-i386: Perform set/reset_inhibit_irq inline,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/14] target-i386: Split up gen_lea_modrm, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 08/14] target-i386: Implement BNDMK, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 09/14] target-i386: Implement BNDMOV, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 11/14] target-i386: Update BNDSTATUS for exceptions raised by BOUND, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 12/14] target-i386: Implement BNDLDX, BNDSTX, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 10/14] target-i386: Implement BNDCL, BNDCU, BNDCN, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 13/14] target-i386: Clear bndregs during legacy near jumps, Richard Henderson, 2015/07/09
- [Qemu-devel] [PATCH 14/14] target-i386: Enable XCR0 features for user-mode, Richard Henderson, 2015/07/09