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[Qemu-devel] [PATCH] target-mips: update mips32r5-generic into P5600
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH] target-mips: update mips32r5-generic into P5600 |
Date: |
Fri, 10 Jul 2015 12:10:52 +0100 |
As full specification of P5600 is available, mips32r5-generic should
be renamed to P5600 and corrected as its intention.
Correct PRid and detail of configuration.
Features which are not currently supported are described as FIXME.
Fix Config.MM bit location
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/cpu.h | 2 +-
target-mips/translate_init.c | 51 +++++++++++++++++++++++-------------------
2 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 075c561..c91883d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -395,7 +395,7 @@ struct CPUMIPSState {
#define CP0C0_K23 28
#define CP0C0_KU 25
#define CP0C0_MDU 20
-#define CP0C0_MM 17
+#define CP0C0_MM 18
#define CP0C0_BM 16
#define CP0C0_BE 15
#define CP0C0_AT 13
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 9304e74..e3d398e 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -389,39 +389,44 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
- /* A generic CPU providing MIPS32 Release 5 features.
- FIXME: Eventually this should be replaced by a real CPU model. */
- .name = "mips32r5-generic",
- .CP0_PRid = 0x00019700,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ /* FIXME:
+ * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
+ * Config4: MMUExtDef
+ * Config5: EVA, MRP
+ * FIR(FCR0): Has2008
+ * */
+ .name = "P5600",
+ .CP0_PRid = 0x0001A800,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
+ .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 < CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
- (1 << CP0C3_LPA),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+ (0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) |
- (1 << CP0C5_MVH),
- .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
- (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
- (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
- (0 << CP0C5_NFExists),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3778FF1F,
- .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
- .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
- (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
- (0x93 << FCR0_PRID),
+ .CP0_Status_rw_bitmask = 0x3C68FF1F,
+ .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
+ (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x03 << FCR0_PRID),
.SEGBITS = 32,
.PABITS = 40,
- .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
+ .insn_flags = CPU_MIPS32R5 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
--
1.7.5.4
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