Re: [Qemu-devel] [PATCH 1/6] ARM: add Cortex-M3/M4 exception configuration and status registers

[Peter Maydell]

On 7 July 2015 at 19:25, Alex Zuepke <address@hidden> wrote:
>
> Signed-off-by: Alex Zuepke <address@hidden>
> ---
>  target-arm/cpu.h     |   51 
> ++++++++++++++++++++++++++++++++++++++++++++++++++
>  target-arm/machine.c |    6 ++++++
>  2 files changed, 57 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 80297b3..1089f63 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -387,6 +387,12 @@ typedef struct CPUARMState {
>          uint32_t control;
>          int current_sp;
>          int exception;
> +        uint32_t ccr;
> +        uint32_t cfsr;
> +        uint32_t hfsr;
> +        uint32_t dfsr;
> +        uint32_t mmfar;
> +        uint32_t bfar;
>      } v7m;

Also, the reset value of the CCR (for M3 and M4, at least) is
0x00000200, not 0, so you need to put something in arm_cpu_reset().
Otherwise when you wire up the behaviour of CCR.STACKALIGN in
the later patch we'll break for guests which don't manually
set the bit but rely on it being set.

(Strictly speaking the reset value of the bit is IMPDEF, as
is whether it's RW or RO, but we can leave it common to all
the M profile cores we emulate until we add a core which
needs it to behave differently.)

thanks
-- PMM