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[Qemu-devel] [PATCH RFC 7/9] tcg: replace ext/u_i32_i64 by a mov when no
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH RFC 7/9] tcg: replace ext/u_i32_i64 by a mov when not implemented |
Date: |
Wed, 15 Jul 2015 13:03:17 +0200 |
When ext_i32_i64 and extu_i32_i64 ops are not implemented, this means
that the register is already properly zero/sign extended, so we can
simply replace it by a mov.
In practice it means at least one of the two ops should always be
implemented on 64-bit targets.
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/tcg-op.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c8db812..b4b1654 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1775,7 +1775,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
} else {
/* Note: we assume the target supports move between
32 and 64 bit registers. */
- tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
+ tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
}
}
@@ -1790,7 +1790,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
} else {
/* Note: we assume the target supports move between
32 and 64 bit registers. */
- tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
+ tcg_gen_mov_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
}
}
--
2.1.4
- [Qemu-devel] [PATCH RFC 1/9] tcg: rename trunc_shr_i32 into trunc_shr_i64_i32, (continued)
[Qemu-devel] [PATCH RFC 7/9] tcg: replace ext/u_i32_i64 by a mov when not implemented,
Aurelien Jarno <=
[Qemu-devel] [PATCH RFC 9/9] tcg: update README about size changing ops, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 4/9] tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 6/9] tcg/i386: document the way 32/64-bit conversions are handled, Aurelien Jarno, 2015/07/15