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[Qemu-devel] [PULL 2/9] target-mips: fix to clear MSACSR.Cause
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 2/9] target-mips: fix to clear MSACSR.Cause |
Date: |
Thu, 16 Jul 2015 09:17:30 +0100 |
From: Yongbok Kim <address@hidden>
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/msa_helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index 26ffdc7..a1cb48f 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/msa_helper.c
@@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
--
2.1.0
- [Qemu-devel] [PULL 0/9] target-mips queue, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 1/9] target-mips: fix MIPS64R6-generic configuration, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 4/9] target-mips: fix ASID synchronisation for MIPS MT, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 2/9] target-mips: fix to clear MSACSR.Cause,
Leon Alrae <=
- [Qemu-devel] [PULL 3/9] disas/mips: fix disassembling R6 instructions, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 5/9] target-mips: correct DERET instruction, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 6/9] target-mips: fix logically dead code reported by Coverity, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 7/9] target-mips: fix resource leak reported by Coverity, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 9/9] target-mips: fix page fault address for LWL/LWR/LDL/LDR, Leon Alrae, 2015/07/16
- [Qemu-devel] [PULL 8/9] linux-user: Fix MIPS N64 trap and break instruction bug, Leon Alrae, 2015/07/16
- Re: [Qemu-devel] [PULL 0/9] target-mips queue, Peter Maydell, 2015/07/16