[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 6/6] ARM: enable PMSAv7-style MPU on Cortex-M3/M
|
From: |
Peter Maydell |
|
Subject: |
Re: [Qemu-devel] [PATCH 6/6] ARM: enable PMSAv7-style MPU on Cortex-M3/M4 |
|
Date: |
Thu, 16 Jul 2015 11:26:09 +0100 |
On 15 July 2015 at 08:31, Alex Züpke <address@hidden> wrote:
> Am 14.07.2015 um 19:49 schrieb Peter Maydell:
>> RASR is UNPREDICTABLE for non-word-size access, so we don't need
>> this at all.
>
> It's from ARM recommended sample code:
> http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/BIHHHDDJ.html
Ah, thanks. It turns out that this is a difference between
implementations: earlier M profile cores (M3, M4) support
byte and halfword accesses here, but later ones don't, so
the architecture defines it as UNPREDICTABLE. Since we're
modelling an M3, it's probably safest to implement it.
You might find that extract32()/deposit32() make for a
cleaner way to write it, though.
-- PMM