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Re: [Qemu-devel] [PATCH RFC 8/9] tcg/optimize: do not simplify size chan
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH RFC 8/9] tcg/optimize: do not simplify size changing moves |
Date: |
Fri, 17 Jul 2015 12:33:21 +0200 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On 2015-07-17 07:38, Richard Henderson wrote:
> On 07/15/2015 12:03 PM, Aurelien Jarno wrote:
> >Now that we have real size changing ops, we don't need to marked high
> >bits of the destination as garbage. The goal of the optimizer is to
> >predict the value of the temps (and not of the registers) and do
> >simplifications when possible. The problem there is therefore not the
> >fact that those bits are not counted as garbage, but that a size
> >changing op is replaced by a move.
> >
> >This patch is basically a revert of 24666baf, including the changes that
> >have been made since then.
> >
> >Cc: Paolo Bonzini <address@hidden>
> >Cc: Richard Henderson <address@hidden>
> >Signed-off-by: Aurelien Jarno <address@hidden>
>
> What we're missing here is whether the omitted size changing op is extu or
> exts. Mask should be extended to match. Which means keeping most of this
> code.
I am afraid your correct. Unfortunately one of my goal is to remove this
part in the optimizer, as I need that in a patch series I am preparing.
I have also tried to check the temp type directly from the optimizer (it
is accessible), but it has some performance impact. Propagating the
extu/exts as real opcode means propagating the information about size
changing up to the optimizer or the register allocator, without having
to recreate it from other available information.
For now I do wonder if we shouldn't get the size changing extu/exts
mandatory instead of reusing the 64-bit only version. This doesn't
change the generated code, at least on x86.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH RFC 0/9] tcg: improve size changing ops, Aurelien Jarno, 2015/07/15
- [Qemu-devel] [PATCH RFC 2/9] tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32, Aurelien Jarno, 2015/07/15
- [Qemu-devel] [PATCH RFC 1/9] tcg: rename trunc_shr_i32 into trunc_shr_i64_i32, Aurelien Jarno, 2015/07/15
- [Qemu-devel] [PATCH RFC 3/9] tcg: implement real ext_i32_i64 and extu_i32_i64 ops, Aurelien Jarno, 2015/07/15
- [Qemu-devel] [PATCH RFC 5/9] tcg/i386: implement ext_i32_i64 and extu_i32_i64 ops, Aurelien Jarno, 2015/07/15
- [Qemu-devel] [PATCH RFC 8/9] tcg/optimize: do not simplify size changing moves, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 7/9] tcg: replace ext/u_i32_i64 by a mov when not implemented, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 9/9] tcg: update README about size changing ops, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 4/9] tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops, Aurelien Jarno, 2015/07/15
[Qemu-devel] [PATCH RFC 6/9] tcg/i386: document the way 32/64-bit conversions are handled, Aurelien Jarno, 2015/07/15