[Qemu-devel] [PATCH v3 16/35] cpu-defs: Allow multiple inclusions

[Peter Crosthwaite]

Allow subsequent inclusion of cpu-defs.h. This allows including
multiple cpu.h's and each getting the right set of definitions for
its env structure definition. All defined symbols are undeffed and
redeffed to the new values.

CPUTLBEntry and CPUIOTLBEntry are defined as types so each needs some
special handling. CPUIOTLBEntry has no arch specifics so it doesn't need
redefinition. Just use a regular multi-include guard around this def.
CPUTLBEntry is handled by not defining the struct type for multi-arch
and instead putting an equivalent sized uint8_t dummy array in the env.
This is ok, because multi-arch code is the only code allowed to multi
include cpu.h and the same time, the multi-arch core is not allowed
to access this struct and its fields.

With this patch, 1 << CPU_TLB_ENTRY_BITS would have 4 usages, so define
CPU_TLB_ENTRY_SIZE for convenience and replace existing candidate
users.

Signed-off-by: Peter Crosthwaite <address@hidden>
---
Changed since RFC v2:
Handle structs to avoid need for user renaming.
---
 include/exec/cpu-defs.h | 63 ++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 47 insertions(+), 16 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 3889eb7..66cc755 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -16,8 +16,10 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
-#ifndef CPU_DEFS_H
-#define CPU_DEFS_H
+
+/* No multiple include guard intended. Multi-arch setups may require multiple
+ * cpu.h's included which means this can be and should be reached twice.
+ */
 
 #ifndef NEED_CPU_H
 #error cpu.h included from common code
@@ -35,16 +37,25 @@
 
 #include "exec/target-long.h"
 
+#undef CPU_COMMON
+#undef CPU_COMMON_TLB
+
 #if !defined(CONFIG_USER_ONLY)
+
+#undef CPU_VTLB_SIZE
 /* use a fully associative victim tlb of 8 entries */
 #define CPU_VTLB_SIZE 8
 
+#undef CPU_TLB_ENTRY_BITS
 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
 #define CPU_TLB_ENTRY_BITS 4
 #else
 #define CPU_TLB_ENTRY_BITS 5
 #endif
 
+#undef CPU_TLB_ENTRY_SIZE
+#define CPU_TLB_ENTRY_SIZE (1 << (CPU_TLB_ENTRY_BITS))
+
 /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that
  * the TLB is not unnecessarily small, but still small enough for the
  * TLB lookup instruction sequence used by the TCG target.
@@ -67,6 +78,10 @@
  * 0x18 (the offset of the addend field in each TLB entry) plus the offset
  * of tlb_table inside env (which is non-trivial but not huge).
  */
+
+#undef CPU_TLB_BITS
+#undef CPU_TLB_SIZE
+
 #define CPU_TLB_BITS                                             \
     MIN(8,                                                       \
         TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
@@ -77,6 +92,25 @@
 
 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
 
+/* CPUIOTLBEntry is not arch variable. So don't multi include it */
+
+#ifndef HAVE_CPU_IO_TLB_ENTRY_DEF
+#define HAVE_CPU_IO_TLB_ENTRY_DEF
+
+/* The IOTLB is not accessed directly inline by generated TCG code,
+ * so the CPUIOTLBEntry layout is not as critical as that of the
+ * CPUTLBEntry. (This is also why we don't want to combine the two
+ * structs into one.)
+ */
+typedef struct CPUIOTLBEntry {
+    hwaddr addr;
+    MemTxAttrs attrs;
+} CPUIOTLBEntry;
+
+#endif
+
+#ifndef TARGET_MULTI
+
 typedef union CPUTLBEntry {
     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
@@ -93,25 +127,23 @@ typedef union CPUTLBEntry {
         uintptr_t addend;
     };
     /* padding to get a power of two size */
-    uint8_t dummy[1 << CPU_TLB_ENTRY_BITS];
+    uint8_t dummy[CPU_TLB_ENTRY_SIZE];
 } CPUTLBEntry;
 
-QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
+QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (CPU_TLB_ENTRY_SIZE));
 
-/* The IOTLB is not accessed directly inline by generated TCG code,
- * so the CPUIOTLBEntry layout is not as critical as that of the
- * CPUTLBEntry. (This is also why we don't want to combine the two
- * structs into one.)
- */
-typedef struct CPUIOTLBEntry {
-    hwaddr addr;
-    MemTxAttrs attrs;
-} CPUIOTLBEntry;
+#define CPU_COMMON_TLB_ENTRY                                                \
+    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                      \
+    CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE];
+#else
+#define CPU_COMMON_TLB_ENTRY                                                \
+    uint8_t tlb_table[NB_MMU_MODES][CPU_TLB_SIZE][CPU_TLB_ENTRY_SIZE];      \
+    uint8_t tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE][CPU_TLB_ENTRY_SIZE];
+#endif
 
 #define CPU_COMMON_TLB \
     /* The meaning of the MMU modes is defined in the target code. */   \
-    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
-    CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE];               \
+    CPU_COMMON_TLB_ENTRY                                                \
     CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE];                    \
     CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE];                 \
     target_ulong tlb_flush_addr;                                        \
@@ -129,4 +161,3 @@ typedef struct CPUIOTLBEntry {
     /* soft mmu support */                                              \
     CPU_COMMON_TLB                                                      \
 
-#endif
-- 
1.9.1