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Re: [Qemu-devel] [PATCH 1/4] target-arm: Add the AArch64 view of the Sec
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 1/4] target-arm: Add the AArch64 view of the Secure physical timer |
Date: |
Fri, 24 Jul 2015 11:06:01 +0100 |
On 24 July 2015 at 10:48, Edgar E. Iglesias <address@hidden> wrote:
> On Thu, Jul 16, 2015 at 12:47:26PM +0100, Peter Maydell wrote:
>> + { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
>> + .type = ARM_CP_IO,
>> + .accessfn = gt_stimer_access,
>> + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
>> + .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
> I think you've missed a .access = PL1_RW here. With that change the series
> passes my sectimer tests.
Yep, you're right, this needs to be folded into this patch:
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1679,7 +1679,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
{ .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
- .type = ARM_CP_IO,
+ .type = ARM_CP_IO, .access = PL1_RW,
.accessfn = gt_stimer_access,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
.writefn = gt_sec_cval_write, .raw_writefn = raw_write,
(I won't bother resending unless there are other fixes that need
to be made too.)
thanks
-- PMM