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[Qemu-devel] [PATCH for-2.5 3/5] target-sh4: improve cmp/str instruction
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH for-2.5 3/5] target-sh4: improve cmp/str instruction |
Date: |
Fri, 24 Jul 2015 13:14:29 +0200 |
Instead of testing bytes one by one, we can use the following trick
from https://graphics.stanford.edu/~seander/bithacks.html:
haszero(v) = (v - 0x01010101) & ~v & 0x80808080
The subexpression v - 0x01010101, evaluates to a high bit set in any
byte whenever the corresponding byte in v is zero or greater than 0x80.
The sub-expression ~v & 0x80808080 evaluates to high bits set in bytes
where the byte of v doesn't have its high bit set (so the byte was less
than 0x80). Finally, by ANDing these two sub-expressions the result is
the high bits set where the bytes in v were zero, since the high bits
set due to a value greater than 0x80 in the first sub-expression are
masked off by the second.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/translate.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index a6f3f59..7d7d5e0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -688,18 +688,11 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv cmp1 = tcg_temp_new();
TCGv cmp2 = tcg_temp_new();
- tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
- tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cmp2, 0);
- tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
- tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
- tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
- tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
- tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
- tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
+ tcg_gen_xor_i32(cmp2, REG(B7_4), REG(B11_8));
+ tcg_gen_subi_i32(cmp1, cmp2, 0x01010101);
+ tcg_gen_andc_i32(cmp1, cmp1, cmp2);
+ tcg_gen_andi_i32(cmp1, cmp1, 0x80808080);
+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0);
tcg_temp_free(cmp2);
tcg_temp_free(cmp1);
}
--
2.1.4
- [Qemu-devel] [PATCH for-2.5 0/5] target-sh4: TCG improvement, Aurelien Jarno, 2015/07/24
- [Qemu-devel] [PATCH for-2.5 4/5] target-sh4: improve shld instruction, Aurelien Jarno, 2015/07/24
- [Qemu-devel] [PATCH for-2.5 2/5] target-sh4: use deposit in swap.b instruction, Aurelien Jarno, 2015/07/24
- [Qemu-devel] [PATCH for-2.5 3/5] target-sh4: improve cmp/str instruction,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 5/5] target-sh4: improve shad instruction, Aurelien Jarno, 2015/07/24
- [Qemu-devel] [PATCH for-2.5 1/5] target-sh4: add flags markups for FP helpers, Aurelien Jarno, 2015/07/24
- Re: [Qemu-devel] [PATCH for-2.5 0/5] target-sh4: TCG improvement, Richard Henderson, 2015/07/24