Re: [Qemu-devel] [PATCH for-2.5 05/10] tcg: rename trunc_shr_i32 into trunc_shr_i64_i32

[Alex Bennée]

Aurelien Jarno <address@hidden> writes:

> The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32,
> and the name in the README doesn't match the name offered to the
> frontends.

I was tempted to suggest just naming it shr_i64_i32 as the truncation
is implicit and the slightly shorter name doesn't mess the formatting up
as much. But then I see we have another usage of trunc so:

Reviewed-by: Alex Bennée <address@hidden>

>
> Always use the long name to make it clear it is a size changing op.
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Aurelien Jarno <address@hidden>
> ---
>  tcg/README               | 2 +-
>  tcg/aarch64/tcg-target.h | 2 +-
>  tcg/i386/tcg-target.h    | 2 +-
>  tcg/ia64/tcg-target.h    | 2 +-
>  tcg/optimize.c           | 6 +++---
>  tcg/ppc/tcg-target.h     | 2 +-
>  tcg/s390/tcg-target.h    | 2 +-
>  tcg/sparc/tcg-target.c   | 4 ++--
>  tcg/sparc/tcg-target.h   | 2 +-
>  tcg/tcg-op.c             | 4 ++--
>  tcg/tcg-opc.h            | 4 ++--
>  tcg/tcg.h                | 2 +-
>  tcg/tci/tcg-target.h     | 2 +-
>  13 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/tcg/README b/tcg/README
> index a550ff1..61b3899 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -314,7 +314,7 @@ This operation would be equivalent to
>  
>    dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
>  
> -* trunc_shr_i32 t0, t1, pos
> +* trunc_shr_i64_i32 t0, t1, pos
>  
>  For 64-bit hosts only, right shift the 64-bit input T1 by POS and
>  truncate to 32-bit output T0.  Depending on the host, this may be
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 8aec04d..dfd8801 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -70,7 +70,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_muls2_i32        0
>  #define TCG_TARGET_HAS_muluh_i32        0
>  #define TCG_TARGET_HAS_mulsh_i32        0
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  
>  #define TCG_TARGET_HAS_div_i64          1
>  #define TCG_TARGET_HAS_rem_i64          1
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 25b5133..dae50ba 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -102,7 +102,7 @@ extern bool have_bmi1;
>  #define TCG_TARGET_HAS_mulsh_i32        0
>  
>  #if TCG_TARGET_REG_BITS == 64
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  #define TCG_TARGET_HAS_div2_i64         1
>  #define TCG_TARGET_HAS_rot_i64          1
>  #define TCG_TARGET_HAS_ext8s_i64        1
> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
> index a04ed81..29902f9 100644
> --- a/tcg/ia64/tcg-target.h
> +++ b/tcg/ia64/tcg-target.h
> @@ -160,7 +160,7 @@ typedef enum {
>  #define TCG_TARGET_HAS_muluh_i64        0
>  #define TCG_TARGET_HAS_mulsh_i32        0
>  #define TCG_TARGET_HAS_mulsh_i64        0
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  
>  #define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
>  #define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 48103b2..56e0a17 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -301,7 +301,7 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg 
> x, TCGArg y)
>      case INDEX_op_shr_i32:
>          return (uint32_t)x >> (y & 31);
>  
> -    case INDEX_op_trunc_shr_i32:
> +    case INDEX_op_trunc_shr_i64_i32:
>      case INDEX_op_shr_i64:
>          return (uint64_t)x >> (y & 63);
>  
> @@ -880,7 +880,7 @@ void tcg_optimize(TCGContext *s)
>              }
>              break;
>  
> -        case INDEX_op_trunc_shr_i32:
> +        case INDEX_op_trunc_shr_i64_i32:
>              mask = (uint64_t)temps[args[1]].mask >> args[2];
>              break;
>  
> @@ -1028,7 +1028,7 @@ void tcg_optimize(TCGContext *s)
>              }
>              goto do_default;
>  
> -        case INDEX_op_trunc_shr_i32:
> +        case INDEX_op_trunc_shr_i64_i32:
>              if (temp_is_const(args[1])) {
>                  tmp = do_constant_folding(opc, temps[args[1]].val, args[2]);
>                  tcg_opt_gen_movi(s, op, args, args[0], tmp);
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 7ce7048..b7e6861 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -77,7 +77,7 @@ typedef enum {
>  #if TCG_TARGET_REG_BITS == 64
>  #define TCG_TARGET_HAS_add2_i32         0
>  #define TCG_TARGET_HAS_sub2_i32         0
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  #define TCG_TARGET_HAS_div_i64          1
>  #define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_rot_i64          1
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 91576d5..50016a8 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -72,7 +72,7 @@ typedef enum TCGReg {
>  #define TCG_TARGET_HAS_muls2_i32        0
>  #define TCG_TARGET_HAS_muluh_i32        0
>  #define TCG_TARGET_HAS_mulsh_i32        0
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  
>  #define TCG_TARGET_HAS_div2_i64         1
>  #define TCG_TARGET_HAS_rot_i64          1
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 1a870a8..b23032b 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -1413,7 +1413,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>      case INDEX_op_ext32u_i64:
>          tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
>          break;
> -    case INDEX_op_trunc_shr_i32:
> +    case INDEX_op_trunc_shr_i64_i32:
>          if (a2 == 0) {
>              tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
>          } else {
> @@ -1533,7 +1533,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
>  
>      { INDEX_op_ext32s_i64, { "R", "r" } },
>      { INDEX_op_ext32u_i64, { "R", "r" } },
> -    { INDEX_op_trunc_shr_i32,  { "r", "R" } },
> +    { INDEX_op_trunc_shr_i64_i32,  { "r", "R" } },
>  
>      { INDEX_op_brcond_i64, { "RZ", "RJ" } },
>      { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index f584de4..336c47f 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -118,7 +118,7 @@ extern bool use_vis3_instructions;
>  #define TCG_TARGET_HAS_muluh_i32        0
>  #define TCG_TARGET_HAS_mulsh_i32        0
>  
> -#define TCG_TARGET_HAS_trunc_shr_i32    1
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 1
>  #define TCG_TARGET_HAS_div_i64          1
>  #define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_rot_i64          0
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 45098c3..61b64db 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -1751,8 +1751,8 @@ void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret, TCGv_i64 
> arg, unsigned count)
>              tcg_gen_mov_i32(ret, TCGV_LOW(t));
>              tcg_temp_free_i64(t);
>          }
> -    } else if (TCG_TARGET_HAS_trunc_shr_i32) {
> -        tcg_gen_op3i_i32(INDEX_op_trunc_shr_i32, ret,
> +    } else if (TCG_TARGET_HAS_trunc_shr_i64_i32) {
> +        tcg_gen_op3i_i32(INDEX_op_trunc_shr_i64_i32, ret,
>                           MAKE_TCGV_I32(GET_TCGV_I64(arg)), count);
>      } else if (count == 0) {
>          tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 13ccb60..4a34f43 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -138,8 +138,8 @@ DEF(rotl_i64, 1, 2, 0, IMPL64 | 
> IMPL(TCG_TARGET_HAS_rot_i64))
>  DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
>  DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
>  
> -DEF(trunc_shr_i32, 1, 1, 1,
> -    IMPL(TCG_TARGET_HAS_trunc_shr_i32)
> +DEF(trunc_shr_i64_i32, 1, 1, 1,
> +    IMPL(TCG_TARGET_HAS_trunc_shr_i64_i32)
>      | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
>  
>  DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 231a781..e7e33b9 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -66,7 +66,7 @@ typedef uint64_t TCGRegSet;
>  
>  #if TCG_TARGET_REG_BITS == 32
>  /* Turn some undef macros into false macros.  */
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  #define TCG_TARGET_HAS_div_i64          0
>  #define TCG_TARGET_HAS_rem_i64          0
>  #define TCG_TARGET_HAS_div2_i64         0
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index cbf3f9b..8b1139b 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -84,7 +84,7 @@
>  #define TCG_TARGET_HAS_mulsh_i32        0
>  
>  #if TCG_TARGET_REG_BITS == 64
> -#define TCG_TARGET_HAS_trunc_shr_i32    0
> +#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
>  #define TCG_TARGET_HAS_bswap16_i64      1
>  #define TCG_TARGET_HAS_bswap32_i64      1
>  #define TCG_TARGET_HAS_bswap64_i64      1

-- 
Alex Bennée