Re: [Qemu-devel] [PATCH 3/5] Implement fw_cfg DMA interface

[Laszlo Ersek]

On 08/07/15 22:40, Kevin O'Connor wrote:
> On Thu, Aug 06, 2015 at 04:59:15PM +0200, Marc Marí wrote:
>> On Thu, 6 Aug 2015 10:47:21 -0400
>> "Kevin O'Connor" <address@hidden> wrote:
>>> Also, it's very unusual to see 32bit writes to an unaligned IO address
>>> - I think two pad bytes should be added so that the offset for the dma
>>> address is at position 4 (instead of 2).
>>
>> This is a PIO port (out), not a MMIO access (write). Maybe I'm wrong,
>> but I don't think it matters to have the port number aligned with the
>> write size.
> 
> There was a thread on misaligned IO accesses recently:
> 
>   http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg05054.html
> 
> Perhaps Stefan knows what the implications of misaligned IO writes
> are.
> 
> I suspect it's better to avoid them.

Unrelated, but I just noticed: in (and since) commit 457ba42878,
ICH9_LPC_GEN_PMCON_1 is read with pci_config_read*w*, but rewritten with
pci_config_write*l*.

Is that intended? (My similar OVMF code writes a word, not a long.)

Thanks
Laszlo