[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH for-2.5 08/30] m68k: update CPU flags management
|
From: |
Laurent Vivier |
|
Subject: |
[Qemu-devel] [PATCH for-2.5 08/30] m68k: update CPU flags management |
|
Date: |
Sun, 9 Aug 2015 22:13:27 +0200 |
Copied from target-i386
Signed-off-by: Laurent Vivier <address@hidden>
---
cpu-exec.c | 6 --
target-m68k/cpu.c | 2 -
target-m68k/cpu.h | 6 +-
target-m68k/helper.c | 34 ++-------
target-m68k/helper.h | 2 +-
target-m68k/translate.c | 195 +++++++++++++++++++++++++++++++-----------------
6 files changed, 136 insertions(+), 109 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 75694f3..4138c27 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -184,12 +184,6 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu,
uint8_t *tb_ptr)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
#if defined(TARGET_I386)
log_cpu_state(cpu, CPU_DUMP_CCOP);
-#elif defined(TARGET_M68K)
- /* ??? Should not modify env state for dumping. */
- cpu_m68k_flush_flags(env, env->cc_op);
- env->cc_op = CC_OP_FLAGS;
- env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
- log_cpu_state(cpu, 0);
#else
log_cpu_state(cpu, 0);
#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index f3f4b71..d4d8c12 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -260,8 +260,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#else
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
- cc->cpu_exec_enter = m68k_cpu_exec_enter;
- cc->cpu_exec_exit = m68k_cpu_exec_exit;
dc->vmsd = &vmstate_m68k_cpu;
cc->gdb_num_core_regs = 18;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index d1c182b..6d1a140 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -123,9 +123,8 @@ int cpu_m68k_exec(CPUState *cpu);
is returned if the signal was handled by the virtual CPU. */
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
void *puc);
-void cpu_m68k_flush_flags(CPUM68KState *, int);
-enum {
+typedef enum {
CC_OP_DYNAMIC, /* Use env->cc_op */
CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
CC_OP_LOGICB, /* CC_DEST = result, CC_SRC = unused */
@@ -146,7 +145,8 @@ enum {
CC_OP_SHIFTB, /* CC_DEST = result, CC_SRC = carry */
CC_OP_SHIFTW, /* CC_DEST = result, CC_SRC = carry */
CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
-};
+ CC_OP_NB,
+} CCOp;
#define CCF_C 0x01
#define CCF_V 0x02
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 200e3fc..c6f5cc0 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -135,9 +135,8 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
/* TODO: Add [E]MAC registers. */
}
-void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
+static uint32_t cpu_m68k_flush_flags(CPUM68KState *env, int op)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
int flags;
uint32_t src;
uint32_t dest;
@@ -205,7 +204,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
flags = 0;
src = env->cc_src;
dest = env->cc_dest;
- switch (cc_op) {
+ switch (op) {
case CC_OP_FLAGS:
flags = dest;
break;
@@ -271,10 +270,9 @@ set_x:
SET_FLAGS_SHIFT(int32_t);
break;
default:
- cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op);
+ g_assert_not_reached();
}
- env->cc_op = CC_OP_FLAGS;
- env->cc_dest = flags;
+ return flags;
}
void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
@@ -798,9 +796,9 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
}
}
-void HELPER(flush_flags)(CPUM68KState *env, uint32_t cc_op)
+uint32_t HELPER(flush_flags)(CPUM68KState *env, uint32_t op)
{
- cpu_m68k_flush_flags(env, cc_op);
+ return cpu_m68k_flush_flags(env, op);
}
uint32_t HELPER(get_macf)(CPUM68KState *env, uint64_t val)
@@ -930,23 +928,3 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val,
uint32_t acc)
res |= (uint64_t)(val & 0xffff0000) << 16;
env->macc[acc + 1] = res;
}
-
-void m68k_cpu_exec_enter(CPUState *cs)
-{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
-
- env->cc_op = CC_OP_FLAGS;
- env->cc_dest = env->sr & 0xf;
- env->cc_x = (env->sr >> 4) & 1;
-}
-
-void m68k_cpu_exec_exit(CPUState *cs)
-{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
-
- cpu_m68k_flush_flags(env, env->cc_op);
- env->cc_op = CC_OP_FLAGS;
- env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
-}
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index f4e5fdf..81c8e79 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -46,5 +46,5 @@ DEF_HELPER_3(set_mac_extf, void, env, i32, i32)
DEF_HELPER_3(set_mac_exts, void, env, i32, i32)
DEF_HELPER_3(set_mac_extu, void, env, i32, i32)
-DEF_HELPER_2(flush_flags, void, env, i32)
+DEF_HELPER_2(flush_flags, i32, env, i32)
DEF_HELPER_2(raise_exception, void, env, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 27cb89c..80ac63a 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -68,6 +68,8 @@ static TCGv NULL_QREG;
/* Used to distinguish stores from bad addressing modes. */
static TCGv store_dummy;
+static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
+
#include "exec/gen-icount.h"
void m68k_tcg_init(void)
@@ -125,7 +127,7 @@ typedef struct DisasContext {
target_ulong insn_pc; /* Start of the current instruction. */
target_ulong pc;
int is_jmp;
- int cc_op;
+ CCOp cc_op; /* Current CC operation */
int user;
uint32_t fpcr;
struct TranslationBlock *tb;
@@ -175,6 +177,53 @@ typedef void (*disas_proc)(CPUM68KState *env, DisasContext
*s, uint16_t insn);
uint16_t insn)
#endif
+enum {
+ USES_CC_DST = 1,
+ USES_CC_SRC = 2,
+};
+
+static const uint8_t cc_op_live[CC_OP_NB] = {
+ [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_FLAGS] = USES_CC_DST,
+ [CC_OP_LOGICB ... CC_OP_LOGIC] = USES_CC_DST,
+ [CC_OP_ADDB ... CC_OP_ADD] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_SUBB ... CC_OP_SUB] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_ADDXB ... CC_OP_ADDX] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_SUBXB ... CC_OP_SUBX] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_SHIFTB ... CC_OP_SHIFT] = USES_CC_DST | USES_CC_SRC,
+};
+
+static void set_cc_op(DisasContext *s, CCOp op)
+{
+ int dead;
+
+ if (s->cc_op == op) {
+ return;
+ }
+
+ /* Discard CC computation that will no longer be used. */
+
+ dead = cc_op_live[s->cc_op] & ~cc_op_live[op];
+ if (dead & USES_CC_DST) {
+ tcg_gen_discard_i32(QREG_CC_DEST);
+ }
+ if (dead & USES_CC_SRC) {
+ tcg_gen_discard_i32(QREG_CC_SRC);
+ }
+ if (s->cc_op == CC_OP_DYNAMIC) {
+ tcg_gen_discard_i32(QREG_CC_OP);
+ }
+ s->cc_op = op;
+}
+
+/* Update the CPU env CC_OP state. */
+static inline void update_cc_op(DisasContext *s)
+{
+ if (s->cc_op != CC_OP_DYNAMIC) {
+ tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
+ }
+}
+
/* Generate a load from the specified address. Narrow values are
sign extended to full register width. */
static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
@@ -412,31 +461,28 @@ static TCGv gen_lea_indexed(CPUM68KState *env,
DisasContext *s, TCGv base)
return add;
}
-/* Update the CPU env CC_OP state. */
-static inline void gen_flush_cc_op(DisasContext *s)
-{
- if (s->cc_op != CC_OP_DYNAMIC)
- tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
-}
-
/* Evaluate all the CC flags. */
+
static inline void gen_flush_flags(DisasContext *s)
{
if (s->cc_op == CC_OP_FLAGS)
return;
- gen_flush_cc_op(s);
- gen_helper_flush_flags(cpu_env, QREG_CC_OP);
- s->cc_op = CC_OP_FLAGS;
+ if (s->cc_op == CC_OP_DYNAMIC) {
+ gen_helper_flush_flags(QREG_CC_DEST, cpu_env, QREG_CC_OP);
+ } else {
+ gen_helper_flush_flags(QREG_CC_DEST, cpu_env, tcg_const_i32(s->cc_op));
+ }
+ set_cc_op(s, CC_OP_FLAGS);
}
#define SET_CC_OP(opsize, op) do { \
switch (opsize) { \
case OS_BYTE: \
- s->cc_op = CC_OP_##op##B; break; \
+ set_cc_op(s, CC_OP_##op##B); break; \
case OS_WORD: \
- s->cc_op = CC_OP_##op##W; break; \
+ set_cc_op(s, CC_OP_##op##W); break; \
case OS_LONG: \
- s->cc_op = CC_OP_##op; break; \
+ set_cc_op(s, CC_OP_##op); break; \
default: \
abort(); \
} \
@@ -865,7 +911,7 @@ DISAS_INSN(scc)
/* Force a TB lookup after an instruction that changes the CPU state. */
static void gen_lookup_tb(DisasContext *s)
{
- gen_flush_cc_op(s);
+ update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, s->pc);
s->is_jmp = DISAS_UPDATE;
}
@@ -873,7 +919,7 @@ static void gen_lookup_tb(DisasContext *s)
/* Generate a jump to an immediate address. */
static void gen_jmp_im(DisasContext *s, uint32_t dest)
{
- gen_flush_cc_op(s);
+ update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
@@ -881,14 +927,14 @@ static void gen_jmp_im(DisasContext *s, uint32_t dest)
/* Generate a jump to the address in qreg DEST. */
static void gen_jmp(DisasContext *s, TCGv dest)
{
- gen_flush_cc_op(s);
+ update_cc_op(s);
tcg_gen_mov_i32(QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
static void gen_exception(DisasContext *s, uint32_t where, int nr)
{
- gen_flush_cc_op(s);
+ update_cc_op(s);
gen_jmp_im(s, where);
gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
}
@@ -1000,7 +1046,7 @@ DISAS_INSN(divw)
tcg_gen_ext16u_i32(tmp, QREG_DIV1);
tcg_gen_shli_i32(src, QREG_DIV2, 16);
tcg_gen_or_i32(reg, tmp, src);
- s->cc_op = CC_OP_FLAGS;
+ set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(divl)
@@ -1032,7 +1078,7 @@ DISAS_INSN(divl)
/* rem */
tcg_gen_mov_i32 (reg, QREG_DIV2);
}
- s->cc_op = CC_OP_FLAGS;
+ set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(addsub)
@@ -1057,11 +1103,11 @@ DISAS_INSN(addsub)
if (add) {
tcg_gen_add_i32(dest, tmp, src);
gen_helper_xflag_lt(QREG_CC_X, dest, src);
- s->cc_op = CC_OP_ADD;
+ set_cc_op(s, CC_OP_ADD);
} else {
gen_helper_xflag_lt(QREG_CC_X, tmp, src);
tcg_gen_sub_i32(dest, tmp, src);
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
}
gen_update_cc_add(dest, src);
if (insn & 0x100) {
@@ -1248,7 +1294,6 @@ DISAS_INSN(bitop_im)
DEST_EA(env, insn, opsize, tmp, &addr);
}
}
-
DISAS_INSN(arith_im)
{
int op;
@@ -1275,14 +1320,14 @@ DISAS_INSN(arith_im)
gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
tcg_gen_subi_i32(dest, dest, im);
gen_update_cc_add(dest, tcg_const_i32(im));
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
break;
case 3: /* addi */
tcg_gen_mov_i32(dest, src1);
tcg_gen_addi_i32(dest, dest, im);
gen_update_cc_add(dest, tcg_const_i32(im));
gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
- s->cc_op = CC_OP_ADD;
+ set_cc_op(s, CC_OP_ADD);
break;
case 5: /* eori */
tcg_gen_xori_i32(dest, src1, im);
@@ -1292,7 +1337,7 @@ DISAS_INSN(arith_im)
tcg_gen_mov_i32(dest, src1);
tcg_gen_subi_i32(dest, dest, im);
gen_update_cc_add(dest, tcg_const_i32(im));
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
break;
default:
abort();
@@ -1409,10 +1454,10 @@ DISAS_INSN(neg)
src1 = tcg_temp_new();
tcg_gen_mov_i32(src1, reg);
tcg_gen_neg_i32(reg, src1);
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
gen_update_cc_add(reg, src1);
gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
@@ -1422,39 +1467,33 @@ static void gen_set_sr_im(DisasContext *s, uint16_t
val, int ccr_only)
if (!ccr_only) {
gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
}
+ set_cc_op(s, CC_OP_FLAGS);
}
-static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
- int ccr_only)
+static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{
TCGv tmp;
- TCGv reg;
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(QREG_CC_DEST, val, 0xf);
+ tcg_gen_shri_i32(tmp, val, 4);
+ tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
+ if (!ccr_only) {
+ gen_helper_set_sr(cpu_env, val);
+ }
+}
+static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
+ int ccr_only)
+{
+ TCGv src;
s->cc_op = CC_OP_FLAGS;
- if ((insn & 0x38) == 0)
- {
- tmp = tcg_temp_new();
- reg = DREG(insn, 0);
- tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
- tcg_gen_shri_i32(tmp, reg, 4);
- tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
- if (!ccr_only) {
- gen_helper_set_sr(cpu_env, reg);
- }
- }
- else if ((insn & 0x3f) == 0x3c)
- {
- uint16_t val;
- val = read_im16(env, s);
- gen_set_sr_im(s, val, ccr_only);
- }
- else
- disas_undef(env, s, insn);
+ SRC_EA(env, src, OS_WORD, 0, NULL);
+ gen_set_sr(s, src, ccr_only);
}
DISAS_INSN(move_to_ccr)
{
- gen_set_sr(env, s, insn, 1);
+ gen_move_to_sr(env, s, insn, 1);
}
DISAS_INSN(not)
@@ -1659,11 +1698,11 @@ DISAS_INSN(addsubq)
if (insn & 0x0100) {
gen_helper_xflag_lt(QREG_CC_X, dest, src2);
tcg_gen_subi_i32(dest, dest, val);
- s->cc_op = CC_OP_SUB;
+ set_cc_op(s, CC_OP_SUB);
} else {
tcg_gen_addi_i32(dest, dest, val);
gen_helper_xflag_lt(QREG_CC_X, dest, src2);
- s->cc_op = CC_OP_ADD;
+ set_cc_op(s, CC_OP_ADD);
}
gen_update_cc_add(dest, src2);
}
@@ -1706,16 +1745,18 @@ DISAS_INSN(branch)
/* bsr */
gen_push(s, tcg_const_i32(s->pc));
}
- gen_flush_cc_op(s);
if (op > 1) {
/* Bcc */
l1 = gen_new_label();
gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
+ update_cc_op(s);
gen_jmp_tb(s, 1, base + offset);
gen_set_label(l1);
+ update_cc_op(s);
gen_jmp_tb(s, 0, s->pc);
} else {
/* Unconditional branch. */
+ update_cc_op(s);
gen_jmp_tb(s, 0, base + offset);
}
}
@@ -1891,7 +1932,7 @@ DISAS_INSN(addx)
reg = DREG(insn, 9);
src = DREG(insn, 0);
gen_helper_addx_cc(reg, cpu_env, reg, src);
- s->cc_op = CC_OP_FLAGS;
+ set_cc_op(s, CC_OP_FLAGS);
}
/* TODO: This could be implemented without helper functions. */
@@ -1916,7 +1957,7 @@ DISAS_INSN(shift_im)
gen_helper_sar_cc(reg, cpu_env, reg, shift);
}
}
- s->cc_op = CC_OP_SHIFT;
+ set_cc_op(s, CC_OP_SHIFT);
}
DISAS_INSN(shift_reg)
@@ -1937,7 +1978,7 @@ DISAS_INSN(shift_reg)
gen_helper_sar_cc(reg, cpu_env, reg, shift);
}
}
- s->cc_op = CC_OP_SHIFT;
+ set_cc_op(s, CC_OP_SHIFT);
}
DISAS_INSN(ff1)
@@ -1982,16 +2023,14 @@ DISAS_INSN(strldsr)
DISAS_INSN(move_from_sr)
{
- TCGv reg;
TCGv sr;
- if (IS_USER(s)) {
+ if (IS_USER(s)) { /* FIXME: not privileged on 68000 */
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
sr = gen_get_sr(s);
- reg = DREG(insn, 0);
- gen_partset_reg(OS_WORD, reg, sr);
+ DEST_EA(env, insn, OS_WORD, sr, NULL);
}
DISAS_INSN(move_to_sr)
@@ -2000,7 +2039,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
- gen_set_sr(env, s, insn, 0);
+ gen_move_to_sr(env, s, insn, 0);
gen_lookup_tb(s);
}
@@ -2751,7 +2790,7 @@ DISAS_INSN(macsr_to_ccr)
{
tcg_gen_movi_i32(QREG_CC_X, 0);
tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
- s->cc_op = CC_OP_FLAGS;
+ set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(to_mac)
@@ -3107,6 +3146,7 @@ gen_intermediate_code_internal(M68kCPU *cpu,
TranslationBlock *tb,
tcg_ctx.gen_opc_instr_start[lj++] = 0;
}
tcg_ctx.gen_opc_pc[lj] = dc->pc;
+ gen_opc_cc_op[lj] = dc->cc_op;
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
@@ -3126,20 +3166,20 @@ gen_intermediate_code_internal(M68kCPU *cpu,
TranslationBlock *tb,
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
- gen_flush_cc_op(dc);
+ update_cc_op(dc);
tcg_gen_movi_i32(QREG_PC, dc->pc);
}
gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
} else {
switch(dc->is_jmp) {
case DISAS_NEXT:
- gen_flush_cc_op(dc);
+ update_cc_op(dc);
gen_jmp_tb(dc, 0, dc->pc);
break;
default:
case DISAS_JUMP:
case DISAS_UPDATE:
- gen_flush_cc_op(dc);
+ update_cc_op(dc);
/* indicate that the hash table must be used to find the next TB */
tcg_gen_exit_tb(0);
break;
@@ -3168,9 +3208,6 @@ gen_intermediate_code_internal(M68kCPU *cpu,
TranslationBlock *tb,
tb->size = dc->pc - pc_start;
tb->icount = num_insns;
}
-
- //optimize_flags();
- //expand_target_qops();
}
void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
@@ -3208,5 +3245,25 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
{
+ int cc_op;
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
+ int i;
+ qemu_log("RESTORE:\n");
+ for (i = 0; i <= pc_pos; i++) {
+ if (tcg_ctx.gen_opc_instr_start[i]) {
+ qemu_log("0x%04x: " TARGET_FMT_lx "\n", i,
+ tcg_ctx.gen_opc_pc[i]);
+ }
+ }
+ qemu_log("pc_pos=0x%x pc=" TARGET_FMT_lx " CC_OP %d\n",
+ pc_pos, tcg_ctx.gen_opc_pc[pc_pos],
+ gen_opc_cc_op[pc_pos]);
+ }
+#endif
env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+ cc_op = gen_opc_cc_op[pc_pos];
+ if (cc_op != CC_OP_DYNAMIC) {
+ env->cc_op = cc_op;
+ }
}
--
2.4.3
[Qemu-devel] [PATCH for-2.5 17/30] m68k: ori/andi/subi/addi/eori/cmpi can modify SR/CCR, Laurent Vivier, 2015/08/09
[Qemu-devel] [PATCH for-2.5 18/30] m68k: addq/subq can work with all the data sizes., Laurent Vivier, 2015/08/09
[Qemu-devel] [PATCH for-2.5 16/30] m68k: Add all access modes and data sizes to some 680x0 instructions, Laurent Vivier, 2015/08/09