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[Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2 |
Date: |
Thu, 13 Aug 2015 11:44:22 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Adds control for trapping selected timer and counter accesses to EL2.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 33 +++++++++++++++++++++++++++++++--
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b1fa287..ea41052 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -358,6 +358,7 @@ typedef struct CPUARMState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
+ uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b8188ad..3f8d06e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1154,23 +1154,41 @@ static CPAccessResult gt_cntfrq_access(CPUARMState
*env, const ARMCPRegInfo *ri)
static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
return CP_ACCESS_TRAP;
}
+
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 0, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
return CP_ACCESS_OK;
}
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
* EL0[PV]TEN is zero.
*/
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
return CP_ACCESS_TRAP;
}
+
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
return CP_ACCESS_OK;
}
@@ -2631,6 +2649,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
.resetvalue = 0 },
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2749,6 +2770,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vaa_write },
#ifndef CONFIG_USER_ONLY
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
+ * reset values as IMPDEF. We choose to reset to 3 to comply with
+ * both ARMv7 and ARMv8.
+ */
+ .access = PL2_RW, .resetvalue = 3,
+ .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
--
1.9.1
- [Qemu-devel] [PULL 22/27] target-arm: Add debug check for mismatched cpreg resets, (continued)
- [Qemu-devel] [PULL 22/27] target-arm: Add debug check for mismatched cpreg resets, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 23/27] target-arm: Add the AArch64 view of the Secure physical timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 12/27] i.MX: Fix Coding style for AVIC emulator., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 15/27] i.MX: Split EPIT emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 17/27] i.MX: Split GPT emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 24/27] target-arm: Add AArch32 banked register access to secure physical timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 10/27] i.MX:Fix Coding style for UART emulator., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 20/27] hw/arm/gic: Kill code duplication, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 06/27] hw/arm/virt: Replace magic IRQ constants with macros, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 19/27] Merge memory_region_init_reservation() into memory_region_init_io(), Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2,
Peter Maydell <=
- [Qemu-devel] [PULL 14/27] i.MX: Fix Coding style for CCM emulator, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized "chardev" device, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 07/27] hw/arm/virt: Connect the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 11/27] i.MX: Split AVIC emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 13/27] i.MX: Split CCM emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 08/27] i.MX: Split UART emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 05/27] target-arm: Add the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 21/27] Introduce gic_class_name() instead of repeating condition, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt, Peter Maydell, 2015/08/13