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Re: [Qemu-devel] [PATCH 1/6] cputlb: Add functions for flushing TLB for
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 1/6] cputlb: Add functions for flushing TLB for a single MMU index |
Date: |
Fri, 14 Aug 2015 11:24:45 +0100 |
On 7 August 2015 at 13:33, Peter Maydell <address@hidden> wrote:
> Guest CPU TLB maintenance operations may be sufficiently
> specialized to only need to flush TLB entries corresponding
> to a particular MMU index. Implement cputlb functions for
> this, to avoid the inefficiency of flushing TLB entries
> which we don't need to.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> cputlb.c | 81
> +++++++++++++++++++++++++++++++++++++++++++++++++
> include/exec/exec-all.h | 47 ++++++++++++++++++++++++++++
> 2 files changed, 128 insertions(+)
>
> diff --git a/cputlb.c b/cputlb.c
> index a506086..a1996ba 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -69,6 +69,39 @@ void tlb_flush(CPUState *cpu, int flush_global)
> tlb_flush_count++;
> }
>
> +static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
> +{
> + CPUArchState *env = cpu->env_ptr;
> +
> +#if defined(DEBUG_TLB)
> + printf("tlb_flush_by_mmuidx %d:\n", mmu_idx);
> +#endif
This debug tracing doesn't compile if enabled -- it was written
to go with my initial implementation which took a single
mmu_idx rather than varargs, and I forgot to update it. I'll
send out a v2 shortly.
thanks
-- PMM
- [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops, Peter Maydell, 2015/08/07
- [Qemu-devel] [PATCH 1/6] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/07
- Re: [Qemu-devel] [PATCH 1/6] cputlb: Add functions for flushing TLB for a single MMU index,
Peter Maydell <=
- [Qemu-devel] [PATCH 4/6] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/07
- [Qemu-devel] [PATCH 6/6] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/07
- [Qemu-devel] [PATCH 3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/07
- [Qemu-devel] [PATCH 5/6] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/07
- [Qemu-devel] [PATCH 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order, Peter Maydell, 2015/08/07
- Re: [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops, Edgar E. Iglesias, 2015/08/13