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[Qemu-devel] [PATCH 09/11] target-m68k: Optimize gen_flush_flags
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/11] target-m68k: Optimize gen_flush_flags |
Date: |
Fri, 14 Aug 2015 07:59:24 -0700 |
---
target-m68k/translate.c | 56 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 6f60c6f..19097c2 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -461,18 +461,66 @@ static TCGv gen_lea_indexed(CPUM68KState *env,
DisasContext *s, TCGv base)
static void gen_flush_flags(DisasContext *s)
{
- TCGv tmp;
+ TCGv t0, t1;
switch (s->cc_op) {
case CC_OP_FLAGS:
return;
+
+ case CC_OP_ADD:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for addition. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_SUB:
+ tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
+ tcg_temp_free(t1);
+ break;
+
+ case CC_OP_CMP:
+ tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
+ tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
+ /* Compute signed overflow for subtraction. */
+ t0 = tcg_temp_new();
+ tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
+ tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
+ tcg_temp_free(t0);
+ tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
+ break;
+
+ case CC_OP_LOGIC:
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ break;
+
case CC_OP_DYNAMIC:
gen_helper_flush_flags(cpu_env, QREG_CC_OP);
break;
+
default:
- tmp = tcg_const_i32(s->cc_op);
- gen_helper_flush_flags(cpu_env, tmp);
- tcg_temp_free(tmp);
+ t0 = tcg_const_i32(s->cc_op);
+ gen_helper_flush_flags(cpu_env, t0);
+ tcg_temp_free(t0);
break;
}
--
2.4.3
- [Qemu-devel] [PATCH 00/11] Proposed format for m68k flags, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 01/11] target-m68k: Print flags properly, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 02/11] target-m68k: Some fixes to SR and flags management, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 03/11] target-m68k: Remove incorrect clearing of cc_x, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 04/11] target-m68k: Replace helper_xflag_lt with setcond, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 07/11] target-m68k: Use setcond for scc, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 08/11] target-m68k: Optimize some comparisons, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 09/11] target-m68k: Optimize gen_flush_flags,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/11] target-m68k: Inline shifts, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 06/11] target-m68k: Introduce DisasCompare, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 11/11] target-m68k: Inline addx, subx, negx, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 05/11] target-m68k: Reorg flags handling, Richard Henderson, 2015/08/14
- Re: [Qemu-devel] [PATCH 00/11] Proposed format for m68k flags, Laurent Vivier, 2015/08/14