Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Edgar E. Iglesias]

On Fri, Aug 14, 2015 at 11:12:55AM +0100, Peter Maydell wrote:
> Ping?
> 

Hi! Sorry for the delay! I'll have a look at this over the weekend.
Do you happen to have the patches all applied in a branch somewhere?

Thanks,
Edgar


> thanks
> -- PMM
> 
> On 30 July 2015 at 19:36, Peter Maydell <address@hidden> wrote:
> > This series adds a handful of EL3 system registers that
> > we were missing. It also includes the EL2 flavours
> > where there were obvious easy parallels. I think this
> > means we now have all the EL3 sysregs we care about.
> > (A previous series added missing address translation
> > operations; I still have to do the missing TLB ops.)
> >
> > None of these registers are exciting; they're all either
> > reads-as-written or RAZ/WI.
> >
> > A note for people who care about EL2: I notice that a
> > lot of AArch32 EL2 registers have the access permission
> > pattern of "accessible from EL2(NS) and from EL3 if
> > SCR.NS==1, but traps if accessed from EL3 if SCR.NS==0".
> > We don't implement this wrinkle (we won't trap the
> > erroneous EL3 access). This is true of the EL2 regs I
> > add here, but then it's true of all our existing ones...
> >
> > Peter Maydell (4):
> >   target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
> >   target-arm: Implement missing AMAIR registers
> >   target-arm: Implement missing AFSR registers
> >   target-arm: Implement missing ACTLR registers
> >
> >  target-arm/helper.c | 74 
> > ++++++++++++++++++++++++++++++++++++++++++++++++-----
> >  1 file changed, 68 insertions(+), 6 deletions(-)
> >