Re: [Qemu-devel] [PATCH v7 04/11] target-mips: improve exception handling

[Aurelien Jarno]

On 2015-08-13 14:12, Leon Alrae wrote:
> On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
> > @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx, 
> > uint32_t opc, int rt,
> >  #if defined(TARGET_MIPS64)
> >      case OPC_SCD:
> >      case R6_OPC_SCD:
> > -        save_cpu_state(ctx, 1);
> >          op_st_scd(t1, t0, rt, ctx);
> >          opn = "scd";
> >          break;
> >  #endif
> >      case OPC_SC:
> >      case R6_OPC_SC:
> > -        save_cpu_state(ctx, 1);
> >          op_st_sc(t1, t0, rt, ctx);
> >          opn = "sc";
> >          break;
> 
> Wouldn't we be better off assuming that conditional stores in linux-user
> always take an exception (we generate fake EXCP_SC exception) and avoid
> retranslation? After applying these changes I observed significant impact on
> performance in linux-user multithreaded apps, for instance c11-atomic-exec
> test before the change took just 2 seconds to finish, whereas now more than 
> 30...

This really show the impact of retranslation and why we should avoid
it when not necessary. Coming back to the issue here, the fact that we
go through retranslation is actually due to the fact that
helper_raise_exception has been changed to go through retranslation.

Given the code path between user-mode and softmmu is quite different,
we definitely need a different code path wrt exception and retranslation
for the two cases. That said if we want deterministic code execution
(the original purpose of this patch), I don't see how we can do without
forcing retranslation. Pavel, do you have an idea for that?

Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net