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Re: [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 s
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From: |
Christopher Covington |
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Subject: |
Re: [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction |
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Date: |
Wed, 19 Aug 2015 09:19:38 -0700 |
On Aug 13, 2015 9:35 AM, "Peter Maydell" <address@hidden> wrote:
>
> For the A64 instruction set, the semihosting call instruction
> is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
> if semihosting is enabled.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
- [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 2/9] target-arm: Improve semihosting debug prints, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 5/9] include/exec/softmmu-semi.h: Add support for 64-bit values, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 8/9] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 3/9] gdbstub: Implement gdb_do_syscallv(), Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 1/9] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 4/9] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]', Peter Maydell, 2015/08/13
- Re: [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting, Christopher Covington, 2015/08/25