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[Qemu-devel] [PATCH v13r 12/14] target-tilegx: Handle simple logical ope
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v13r 12/14] target-tilegx: Handle simple logical operations |
Date: |
Thu, 20 Aug 2015 22:32:42 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 112 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 109 insertions(+), 3 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 8f3bfc3..2778cde 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -69,6 +69,72 @@ typedef struct {
#include "exec/gen-icount.h"
+/*
+ * All exceptions which can still let working flow continue are all in pipe x1,
+ * which is the last pipe of a bundle. So it is OK to only process the first
+ * exception within a bundle.
+ */
+static void set_exception(DisasContext *dc, int num)
+{
+ if (dc->exception == TILEGX_EXCP_NONE) {
+ dc->exception = num;
+ }
+}
+
+static bool check_gr(DisasContext *dc, uint8_t reg)
+{
+ if (likely(reg < TILEGX_R_COUNT)) {
+ return true;
+ }
+
+ switch (reg) {
+ case TILEGX_R_SN:
+ case TILEGX_R_ZERO:
+ break;
+ case TILEGX_R_IDN0:
+ case TILEGX_R_IDN1:
+ set_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
+ break;
+ case TILEGX_R_UDN0:
+ case TILEGX_R_UDN1:
+ case TILEGX_R_UDN2:
+ case TILEGX_R_UDN3:
+ set_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
+}
+
+static TCGv load_zero(DisasContext *dc)
+{
+ if (TCGV_IS_UNUSED_I64(dc->zero)) {
+ dc->zero = tcg_const_local_i64(0);
+ }
+ return dc->zero;
+}
+
+static TCGv load_gr(DisasContext *dc, unsigned reg)
+{
+ if (check_gr(dc, reg)) {
+ return cpu_regs[reg];
+ }
+ return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, unsigned reg)
+{
+ int n;
+
+ /* Skip the result, mark the exception if necessary, and continue */
+ check_gr(dc, reg);
+
+ n = dc->num_wb++;
+ dc->wb[n].reg = reg;
+ return dc->wb[n].val = tcg_temp_new_i64();
+}
+
/* Differentiate the various pipe encodings. */
#define TY_X0 0
#define TY_X1 1
@@ -104,6 +170,7 @@ static void gen_exception(DisasContext *dc, int num)
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
+ TCGv tdest, tsrca;
const char *mnemonic;
/* Eliminate nops before doing anything else. */
@@ -123,6 +190,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
return TILEGX_EXCP_NONE;
}
+ tdest = dest_gr(dc, dest);
+ tsrca = load_gr(dc, srca);
+
switch (opext) {
case OE_RR_X0(CNTLZ):
case OE_RR_Y0(CNTLZ):
@@ -171,8 +241,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
case OE_RR_Y0(PCNT):
case OE_RR_X0(REVBITS):
case OE_RR_Y0(REVBITS):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X0(REVBYTES):
case OE_RR_Y0(REVBYTES):
+ tcg_gen_bswap64_tl(tdest, tsrca);
+ mnemonic = "revbytes";
+ break;
case OE_RR_X1(SWINT0):
case OE_RR_X1(SWINT1):
case OE_RR_X1(SWINT2):
@@ -198,6 +272,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca, unsigned srcb)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcb = load_gr(dc, srcb);
const char *mnemonic;
switch (opext) {
@@ -211,10 +288,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(ADD, 0, X1):
case OE_RRR(ADD, 0, Y0):
case OE_RRR(ADD, 0, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(AND, 0, X0):
case OE_RRR(AND, 0, X1):
case OE_RRR(AND, 5, Y0):
case OE_RRR(AND, 5, Y1):
+ tcg_gen_and_tl(tdest, tsrca, tsrcb);
+ mnemonic = "and";
+ break;
case OE_RRR(CMOVEQZ, 0, X0):
case OE_RRR(CMOVEQZ, 4, Y0):
case OE_RRR(CMOVNEZ, 0, X0):
@@ -325,14 +406,21 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):
case OE_RRR(NOR, 5, Y1):
+ tcg_gen_nor_tl(tdest, tsrca, tsrcb);
+ mnemonic = "nor";
+ break;
case OE_RRR(OR, 0, X0):
case OE_RRR(OR, 0, X1):
case OE_RRR(OR, 5, Y0):
case OE_RRR(OR, 5, Y1):
+ tcg_gen_or_tl(tdest, tsrca, tsrcb);
+ mnemonic = "or";
+ break;
case OE_RRR(ROTL, 0, X0):
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
@@ -530,10 +618,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(V4SUBSC, 0, X1):
case OE_RRR(V4SUB, 0, X0):
case OE_RRR(V4SUB, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(XOR, 0, X0):
case OE_RRR(XOR, 0, X1):
case OE_RRR(XOR, 5, Y0):
case OE_RRR(XOR, 5, Y1):
+ tcg_gen_xor_tl(tdest, tsrca, tsrcb);
+ mnemonic = "xor";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
@@ -546,6 +638,8 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca, int imm)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
switch (opext) {
@@ -553,8 +647,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
case OE_IM(ADDI, X1):
case OE_IM(ADDXI, X0):
case OE_IM(ADDXI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ case OE(ANDI_OPCODE_Y0, 0, Y0):
+ case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE_IM(ANDI, X0):
case OE_IM(ANDI, X1):
+ tcg_gen_andi_tl(tdest, tsrca, imm);
+ mnemonic = "andi";
+ break;
case OE_IM(CMPEQI, X0):
case OE_IM(CMPEQI, X1):
case OE_IM(CMPLTSI, X0):
@@ -578,8 +678,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
case OE_IM(LWNA_ADD, X1):
case OE_IM(MFSPR, X1):
case OE_IM(MTSPR, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(ORI, X0):
case OE_IM(ORI, X1):
+ tcg_gen_ori_tl(tdest, tsrca, imm);
+ mnemonic = "ori";
+ break;
case OE_IM(ST1_ADD, X1):
case OE_IM(ST2_ADD, X1):
case OE_IM(ST4_ADD, X1):
@@ -612,8 +716,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
case OE_IM(V2MAXSI, X1):
case OE_IM(V2MINSI, X0):
case OE_IM(V2MINSI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(XORI, X0):
case OE_IM(XORI, X1):
+ tcg_gen_xori_tl(tdest, tsrca, imm);
+ mnemonic = "xori";
+ break;
case OE_SH(ROTLI, X0):
case OE_SH(ROTLI, X1):
@@ -656,8 +764,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
case OE(ADDXI_OPCODE_Y1, 0, Y1):
case OE(ADDXLI_OPCODE_X0, 0, X0):
case OE(ADDXLI_OPCODE_X1, 0, X1):
- case OE(ANDI_OPCODE_Y0, 0, Y0):
- case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE(CMPEQI_OPCODE_Y0, 0, Y0):
case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
@@ -962,7 +1068,7 @@ static void notice_excp(DisasContext *dc, uint64_t bundle,
if (likely(excp == TILEGX_EXCP_NONE)) {
return;
}
- dc->exception = excp;
+ set_exception(dc, excp);
if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
}
--
2.4.3
- [Qemu-devel] [PATCH v13r 06/14] target-tilegx: Modify _SPECIAL_ opcodes, (continued)
- [Qemu-devel] [PATCH v13r 06/14] target-tilegx: Modify _SPECIAL_ opcodes, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 01/14] linux-user: tilegx: Firstly add architecture related features, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 07/14] target-tilegx: Add special register information from Tilera Corporation, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 05/14] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 09/14] target-tilegx: Add several helpers for instructions translation, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 08/14] target-tilegx: Add cpu basic features for linux-user, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 04/14] target-tilegx: Add opcode basic implementation from Tilera Corporation, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 11/14] target-tilegx: Add TILE-Gx building files, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 14/14] target-tilegx: Handle most bit manipulation instructions, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 13/14] target-tilegx: Handle arithmetic instructions, Richard Henderson, 2015/08/21
- [Qemu-devel] [PATCH v13r 12/14] target-tilegx: Handle simple logical operations,
Richard Henderson <=
- [Qemu-devel] [PATCH v13r 10/14] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/08/21
- Message not available