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[Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui |
Date: |
Mon, 24 Aug 2015 09:17:58 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e922aee..e417c2a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1175,6 +1175,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
TCGMemOp memop;
+ int i2, i3;
switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
@@ -1369,10 +1370,23 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
unsigned opext,
break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
+ i2 = imm & 7;
+ i3 = 0xff >> i2;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shli_tl(tdest, tdest, i2);
+ mnemonic = "v1shli";
+ break;
case OE_SH(V1SHRSI, X0):
case OE_SH(V1SHRSI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_SH(V1SHRUI, X0):
case OE_SH(V1SHRUI, X1):
+ i2 = imm & 7;
+ i3 = (0xff << i2) & 0xff;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shri_tl(tdest, tdest, i2);
+ mnemonic = "v1shrui";
+ break;
case OE_SH(V2SHLI, X0):
case OE_SH(V2SHLI, X1):
case OE_SH(V2SHRSI, X0):
--
2.4.3
- [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr, (continued)
[Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui,
Richard Henderson <=
[Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs, Richard Henderson, 2015/08/24
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