[Qemu-devel] [PATCH v2 1/2] cpu_arm: Rename 'nvic' to 'irqchip'

[Pavel Fedin]

This name seems to be more appropriate because ARMv8 also needs a link
with GICv3 for CPU interface to work

Signed-off-by: Pavel Fedin <address@hidden>
---
 hw/arm/armv7m.c     |  2 +-
 target-arm/cpu.h    |  5 ++++-
 target-arm/helper.c | 12 ++++++------
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index c6eab6d..19742b7 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -194,7 +194,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int 
mem_size, int num_irq,
 
     nvic = qdev_create(NULL, "armv7m_nvic");
     qdev_prop_set_uint32(nvic, "num-irq", num_irq);
-    env->nvic = nvic;
+    env->irqchip = nvic;
     qdev_init_nofail(nvic);
     sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2e680da..7021b87 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -496,7 +496,10 @@ typedef struct CPUARMState {
         uint32_t *dracr;
     } pmsav7;
 
-    void *nvic;
+    /* Some CPUs have an internal link to their interrupt controller.
+     * Examples are ARMv7m (NVIC) and ARMv8 (GICv3 CPU interface)
+     */
+    DeviceState *irqchip;
     const struct arm_boot_info *boot_info;
 } CPUARMState;
 
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1568aa6..104ac4b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4785,7 +4785,7 @@ static void do_v7m_exception_exit(CPUARMState *env)
 
     type = env->regs[15];
     if (env->v7m.exception != 0)
-        armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
+        armv7m_nvic_complete_irq(env->irqchip, env->v7m.exception);
 
     /* Switch to the target stack.  */
     switch_v7m_sp(env, (type & 4) != 0);
@@ -4841,18 +4841,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
        one we're raising.  */
     switch (cs->exception_index) {
     case EXCP_UDEF:
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        armv7m_nvic_set_pending(env->irqchip, ARMV7M_EXCP_USAGE);
         return;
     case EXCP_SWI:
         /* The PC already points to the next instruction.  */
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
+        armv7m_nvic_set_pending(env->irqchip, ARMV7M_EXCP_SVC);
         return;
     case EXCP_PREFETCH_ABORT:
     case EXCP_DATA_ABORT:
         /* TODO: if we implemented the MPU registers, this is where we
          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
          */
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+        armv7m_nvic_set_pending(env->irqchip, ARMV7M_EXCP_MEM);
         return;
     case EXCP_BKPT:
         if (semihosting_enabled()) {
@@ -4865,10 +4865,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
                 return;
             }
         }
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
+        armv7m_nvic_set_pending(env->irqchip, ARMV7M_EXCP_DEBUG);
         return;
     case EXCP_IRQ:
-        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
+        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->irqchip);
         break;
     case EXCP_EXCEPTION_EXIT:
         do_v7m_exception_exit(env);
-- 
1.9.5.msysgit.0