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[Qemu-devel] [PULL 00/20] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/20] target-arm queue |
Date: |
Tue, 25 Aug 2015 15:59:56 +0100 |
Here's the ARM queue. I know I have a pile of backed-up code
review to do, but I wanted to get these patches out rather
than accumulating a fifty-patch queue...
thanks
-- PMM
The following changes since commit 34a4450434f1a5daee06fca223afcbb9c8f1ee24:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into
staging (2015-08-25 13:34:57 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150825
for you to fetch changes up to ff4657fa18b08279ce1f79da35a0e9e0b9574dd5:
target-arm: Implement AArch64 TLBI operations on IPAs (2015-08-25 15:45:10
+0100)
----------------------------------------------------------------
target-arm queue:
* add missing EL2/EL3 TLBI operations
* add missing EL2/EL3 ATS operations
* add missing EL2/EL3 registers
* update Xilinx MAINTAINERS info
* Xilinx: connect the four OCM banks
* virt: add SMBIOS support
----------------------------------------------------------------
Alistair Francis (3):
xlnx-zynqmp: Connect the four OCM banks
MAINTAINERS: Update Xilinx Maintainership
MAINTAINERS: Add ZynqMP to MAINTAINERS file
Peter Maydell (15):
target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
target-arm: Implement missing AMAIR registers
target-arm: Implement missing AFSR registers
target-arm: Implement missing ACTLR registers
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
target-arm: Enable the AArch32 ATS12NSO ops
target-arm: Implement AArch32 ATS1H* operations
cputlb: Add functions for flushing TLB for a single MMU index
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must
touch
target-arm: Implement missing EL2 TLBI operations
target-arm: Implement missing EL3 TLB invalidate operations
target-arm: Implement AArch64 TLBI operations on IPAs
Wei Huang (2):
smbios: add smbios 3.0 support
smbios: implement smbios support for mach-virt
MAINTAINERS | 27 ++-
cputlb.c | 97 ++++++++
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 26 +++
hw/arm/xlnx-zynqmp.c | 15 ++
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/smbios/smbios.c | 84 +++++--
include/exec/exec-all.h | 47 ++++
include/hw/arm/xlnx-zynqmp.h | 6 +
include/hw/smbios/smbios.h | 51 +++--
qemu-options.hx | 2 +-
target-arm/cpu.h | 3 +
target-arm/helper.c | 489 +++++++++++++++++++++++++++++++++++-----
target-arm/op_helper.c | 8 +
15 files changed, 759 insertions(+), 103 deletions(-)
- [Qemu-devel] [PULL 00/20] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops, Peter Maydell, 2015/08/25