Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles

[Peter Maydell]

On 24 August 2015 at 17:17, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target-tilegx/translate.c | 1145 
> +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 1145 insertions(+)
>  create mode 100644 target-tilegx/translate.c
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> new file mode 100644
> index 0000000..a2d597d
> --- /dev/null
> +++ b/target-tilegx/translate.c
> @@ -0,0 +1,1145 @@
> +/*
> + * QEMU TILE-Gx CPU
> + *
> + *  Copyright (c) 2015 Chen Gang
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "cpu.h"
> +#include "qemu/log.h"
> +#include "disas/disas.h"
> +#include "tcg-op.h"
> +#include "exec/cpu_ldst.h"
> +#include "opcode_tilegx.h"
> +
> +#define FMT64X                          "%016" PRIx64
> +
> +static TCGv_ptr cpu_env;
> +static TCGv cpu_pc;
> +static TCGv cpu_regs[TILEGX_R_COUNT];
> +
> +static const char * const reg_names[64] = {
> +     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
> +     "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
> +    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
> +    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
> +    "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
> +    "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
> +    "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr",
> +    "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
> +};
> +
> +/* Modified registers are cached in temporaries until the end of the bundle. 
> */
> +typedef struct {
> +    unsigned reg;
> +    TCGv val;
> +} DisasContextTemp;
> +
> +#define MAX_WRITEBACK 4
> +
> +/* This is the state at translation time.  */
> +typedef struct {
> +    uint64_t pc;               /* Current pc */
> +
> +    TCGv zero;                  /* For zero register */
> +
> +    DisasContextTemp wb[MAX_WRITEBACK];
> +    int num_wb;
> +    int mmuidx;
> +    bool exit_tb;
> +
> +    struct {
> +        TCGCond cond;    /* branch condition */
> +        TCGv dest;       /* branch destination */
> +        TCGv val1;       /* value to be compared against zero, for cond */
> +    } jmp;               /* Jump object, only once in each TB block */
> +} DisasContext;
> +
> +#include "exec/gen-icount.h"
> +
> +/* Differentiate the various pipe encodings.  */
> +#define TY_X0  0
> +#define TY_X1  1
> +#define TY_Y0  2
> +#define TY_Y1  3
> +
> +/* Remerge the base opcode and extension fields for switching.
> +   The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
> +   Y2 opcode field is 2 bits.  */
> +#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)

Slightly odd to assemble bitfields with multiplies and adds
rather than shifts and logical-or.

> +    qemu_log_mask(CPU_LOG_TB_IN_ASM, "  %" PRIx64 ":  { ", dc->pc);
> +    if (get_Mode(bundle)) {
> +        notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
> +        qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> +        notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
> +        qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> +        notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
> +    } else {
> +        notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
> +        qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> +        notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
> +    }

I notice that even if the first insn in a bundle generates an
exception we'll go ahead and generate unreachable code for
the rest.

I haven't tried to find and compare against any instruction
set documentation, but structurally it looks good, so

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM