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[Qemu-devel] [PATCH v15 27/33] target-tilegx: Handle mask instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v15 27/33] target-tilegx: Handle mask instructions |
Date: |
Wed, 2 Sep 2015 18:31:19 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 1b2ec37..78b87bf 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -643,11 +643,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(FSINGLE_MUL2, 0, X0):
case OE_RRR(FSINGLE_PACK2, 0, X0):
case OE_RRR(FSINGLE_SUB1, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(MNZ, 0, X0):
case OE_RRR(MNZ, 0, X1):
case OE_RRR(MNZ, 4, Y0):
case OE_RRR(MNZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mnz";
+ break;
case OE_RRR(MULAX, 0, X0):
case OE_RRR(MULAX, 3, Y0):
tcg_gen_mul_tl(tdest, tsrca, tsrcb);
@@ -763,7 +767,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mz";
+ break;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):
--
2.4.3
- [Qemu-devel] [PATCH v15 19/33] target-tilegx: Handle unconditional jump instructions, (continued)
- [Qemu-devel] [PATCH v15 19/33] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 20/33] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 25/33] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 21/33] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 22/33] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 24/33] target-tilegx: Handle shift instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 23/33] target-tilegx: Handle bitfield instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 26/33] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 27/33] target-tilegx: Handle mask instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH v15 29/33] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 28/33] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 31/33] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 32/33] target-tilegx: Handle v1shli, v1shrui, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 30/33] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v15 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs, Richard Henderson, 2015/09/02