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[Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling |
Date: |
Fri, 4 Sep 2015 16:05:55 +0100 |
From: Pavel Fedin <address@hidden>
Introduces reusable definitions for CPU affinity masks/shifts and gets rid
of hardcoded magic numbers.
Signed-off-by: Pavel Fedin <address@hidden>
Message-id: address@hidden
[PMM: folded overlong line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 13 +++++++++++++
target-arm/cpu.c | 2 +-
target-arm/kvm32.c | 3 +--
target-arm/kvm64.c | 3 +--
4 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 00c0716..25fb1ce 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -227,6 +227,19 @@ void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+ (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7da29f5..d7b4445 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -456,7 +456,7 @@ static void arm_cpu_initfn(Object *obj)
*/
Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
- cpu->mp_affinity = (Aff1 << 8) | Aff0;
+ cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
#ifndef CONFIG_USER_ONLY
/* Our inbound IRQ and FIQ lines */
diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c
index 421ce0e..3ae57a6 100644
--- a/target-arm/kvm32.c
+++ b/target-arm/kvm32.c
@@ -181,7 +181,6 @@ int kvm_arm_cpreg_level(uint64_t regidx)
return KVM_PUT_RUNTIME_STATE;
}
-#define ARM_MPIDR_HWID_BITMASK 0xFFFFFF
#define ARM_CPU_ID_MPIDR 0, 0, 0, 5
int kvm_arch_init_vcpu(CPUState *cs)
@@ -234,7 +233,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (ret) {
return ret;
}
- cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+ cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
return kvm_arm_init_cpreg_list(cpu);
}
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index bd60889..ceebfeb 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -77,7 +77,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
return true;
}
-#define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFULL
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
int kvm_arch_init_vcpu(CPUState *cs)
@@ -120,7 +119,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (ret) {
return ret;
}
- cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+ cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
return kvm_arm_init_cpreg_list(cpu);
}
--
1.9.1
- [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, (continued)
- [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized CPU affinity handling, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling,
Peter Maydell <=
- [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator., Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv(), Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense, Peter Maydell, 2015/09/04
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/09/07
- [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/09/07