[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC r
|
From: |
Alistair Francis |
|
Subject: |
Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value |
|
Date: |
Fri, 4 Sep 2015 11:32:51 -0700 |
On Fri, Sep 4, 2015 at 11:12 AM, Peter Maydell <address@hidden> wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <address@hidden> wrote:
>> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
>> <address@hidden> wrote:
>>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>>> Bit 15 of the PHY Specific Status Register is reserved and
>>>> should remain 0. Fix the reset value to ensure that the 15th
>>>> bit is not set.
>>>>
>>>> Signed-off-by: Alistair Francis <address@hidden>
>>>
>>> Reviewed-by: Edgar E. Iglesias <address@hidden>
>>
>> Thanks Edgar.
>>
>> Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.
Great! Thanks Peter.
That's fine with me, just thought I would check.
Thanks,
Alistair
>
> -- PMM
>