[Qemu-devel] [PATCH] ARM targets: added ARM_FEATURE for Thumb-exception bit in system control register

[Mike Haben]

Most ARM cores switch unconditionally to ARM mode when an exception 
occurs; some Cortex variants have a "Thumb-exception enable" bit in the 
system control register that allows an unconditional switch to Thumb 
mode instead when handling exceptions.  The presence of this bit seems 
unrelated to the version of instruction set, and some earlier cores use 
the same bit (30) in the control register for a completely different 
purpose, so seems sensible to handle it as yet another ARM feature.

Signed-off-by: Mike Haben <address@hidden>
---
 target-arm/cpu.c    |  4 ++++
 target-arm/cpu.h    |  1 +
 target-arm/helper.c | 17 ++++++++++++-----
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cc6c6f3..9c96fe1 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -933,6 +933,7 @@ static void cortex_r5_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
     set_feature(&cpu->env, ARM_FEATURE_MPU);
+    set_feature(&cpu->env, ARM_FEATURE_SCTLR_TE_BIT);
     cpu->midr = 0x411fc153; /* r1p3 */
     cpu->id_pfr0 = 0x0131;
     cpu->id_pfr1 = 0x001;
@@ -971,6 +972,7 @@ static void cortex_a8_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_SCTLR_TE_BIT);
     cpu->midr = 0x410fc080;
     cpu->reset_fpsid = 0x410330c0;
     cpu->mvfr0 = 0x11110222;
@@ -1045,6 +1047,7 @@ static void cortex_a9_initfn(Object *obj)
      */
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
     set_feature(&cpu->env, ARM_FEATURE_CBAR);
+    set_feature(&cpu->env, ARM_FEATURE_SCTLR_TE_BIT);
     cpu->midr = 0x410fc090;
     cpu->reset_fpsid = 0x41033090;
     cpu->mvfr0 = 0x11110222;
@@ -1107,6 +1110,7 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_SCTLR_TE_BIT);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
     cpu->reset_fpsid = 0x410430f0;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 31825d3..30d49b0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -905,6 +905,7 @@ enum arm_features {
     ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto 
Extensions */
     ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto 
Extensions */
     ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb 
encodings */
+    ARM_FEATURE_SCTLR_TE_BIT, /* Control register bit 30 is 
Thumb-exception */
 };

 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7df1f06..c1c50da 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5658,11 +5658,18 @@ void arm_cpu_do_interrupt(CPUState *cs)
     /* Switch to the new mode, and to the correct instruction set.  */
     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
     env->daif |= mask;
-    /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
-     * and we should just guard the thumb mode on V4 */
-    if (arm_feature(env, ARM_FEATURE_V4T)) {
-        env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & 
SCTLR_TE) != 0;
-    }
+
+    /* Most ARM cores switch unconditionally to ARM mode when an exception
+     * occurs:
+     */
+    env->thumb = false;
+    /* ...but certain cores have a Thumb-exception enable bit in the system
+     * control register:
+     */
+    if (arm_feature(env, ARM_FEATURE_SCTLR_TE_BIT)) {
+         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & 
SCTLR_TE) != 0;
+     }
+
     env->regs[14] = env->regs[15] + offset;
     env->regs[15] = addr;
     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
--
1.9.1