Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode

[Bastian Koppelmann]

On 09/03/2015 02:17 AM, Richard Henderson wrote:
> -        if (dc->mem_idx == MMU_USER_IDX) {
> -            gen_illegal_exception(dc);
> -            return;
> +        {
> +            TCGv_i32 tmp = tcg_temp_new_i32();
> +            tcg_gen_trunc_tl_i32(tmp, cpu_R[ra]);
> +            tcg_gen_ori_i32(tmp, tmp, K16);
> +            gen_helper_mfspr(cpu_R[rd], cpu_env, tmp);
> +            tcg_temp_free_i32(tmp);
>           }
> -        t0 = tcg_const_i32(K16);
> -        gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], t0);
> -        tcg_temp_free(t0);
> -#endif
>           break;

IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and 
the manual is fairly clear about that. User mode cpu ought not to read 
these registers unconditionally.

>   
>       case 0x30:    /* l.mtspr */
>           LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11);
> -#if defined(CONFIG_USER_ONLY)
> -        return;
> -#else
> -        if (dc->mem_idx == MMU_USER_IDX) {
> -            gen_illegal_exception(dc);
> -            return;
> +        {
> +            TCGv_i32 tmp = tcg_temp_new_i32();
> +            tcg_gen_trunc_tl_i32(tmp, cpu_R[ra]);
> +            tcg_gen_ori_i32(tmp, tmp, K5_11);
> +            gen_helper_mtspr(cpu_env, tmp, cpu_R[rb]);
> +            tcg_temp_free_i32(tmp);
>           }
> -        t0 = tcg_const_tl(K5_11);
> -        gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], t0);
> -        tcg_temp_free(t0);
> -#endif
>           break;

Same as above, unconditional write.

Cheers,
Bastian