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Re: [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond fo
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel |
Date: |
Mon, 7 Sep 2015 18:17:57 +0100 |
On 2 September 2015 at 18:57, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target-arm/translate-a64.c | 87
> +++++++++++++++++++++++++++-------------------
> 1 file changed, 51 insertions(+), 36 deletions(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index 1587ab5..dcac490 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -166,6 +166,33 @@ void gen_a64_set_pc_im(uint64_t val)
> tcg_gen_movi_i64(cpu_pc, val);
> }
>
> +typedef struct DisasCompare64 {
> + TCGCond cond;
> + TCGv_i64 value;
> +} DisasCompare64;
> +
> +static void a64_test_cc(DisasCompare64 *c64, int cc)
> +{
> + DisasCompare c32;
> +
> + arm_test_cc(&c32, cc);
> +
> + c64->value = tcg_temp_new_i64();
> + c64->cond = c32.cond;
> + if (c32.cond == TCG_COND_EQ || c32.cond == TCG_COND_NE) {
> + tcg_gen_extu_i32_i64(c64->value, c32.value);
> + } else {
> + tcg_gen_ext_i32_i64(c64->value, c32.value);
> + }
Signed extend would work for EQ and NE as well, wouldn't it?
Why prefer the unsigned extension in those cases? If there's
a reason, it could do with being commented.
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
[Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/02