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Re: [Qemu-devel] [PATCH v1 04/10] target-arm: Add VTCR_EL2


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v1 04/10] target-arm: Add VTCR_EL2
Date: Tue, 8 Sep 2015 15:19:37 +0100

On 3 September 2015 at 21:14, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
>  target-arm/cpu.h    |  1 +
>  target-arm/helper.c | 28 ++++++++++++++++++++++++++--
>  2 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 31825d3..ba22e12 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -223,6 +223,7 @@ typedef struct CPUARMState {
>          };
>          /* MMU translation table base control. */
>          TCR tcr_el[4];
> +        TCR vtcr_el2; /* Virtualization Translation Control.  */
>          uint32_t c2_data; /* MPU data cachable bits.  */
>          uint32_t c2_insn; /* MPU instruction cachable bits.  */
>          union { /* MMU domain access control register
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index a057a70..c82aa1d 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -325,6 +325,21 @@ void init_cpreg_list(ARMCPU *cpu)
>      g_list_free(keys);
>  }
>
> +/*
> + * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
> + * they are accesible when EL3 is using AArch64 regardless of EL3.NS.
> + */
> +static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
> +                                                const ARMCPRegInfo *ri)
> +{
> +    bool secure = arm_is_secure_below_el3(env);
> +
> +    if (secure && !arm_el_is_aa64(env, 3)) {
> +        return CP_ACCESS_TRAP_UNCATEGORIZED;
> +    }
> +    return CP_ACCESS_OK;
> +}

This access function will always return OK for the AArch64 register,
so probably better to split the regdef rather than using STATE_BOTH,
and then avoid the accessfn on the 64-bit register.

> +
>  static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t 
> value)
>  {
>      ARMCPU *cpu = arm_env_get_cpu(env);
> @@ -3112,6 +3127,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },

RAZ/WI register should use CP_CONST/resetvalue=0. (Access functions
apply even for const registers.)

>      { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -3246,6 +3265,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
>        .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
> +    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .writefn = vmsa_tcr_el1_write,

There's no AS bit in the VTCR_EL2, so you could avoid an unnecessary
TLB flush by not using the writefn we use for TCR_EL1. (I think
that if you don't provide a writefn or raw_writefn it should just
work, but check that...)

> +      .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
>      { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
> @@ -5735,8 +5760,7 @@ static inline bool 
> regime_translation_disabled(CPUARMState *env,
>  static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
>  {
>      if (mmu_idx == ARMMMUIdx_S2NS) {
> -        /* TODO: return VTCR_EL2 */
> -        g_assert_not_reached();
> +        return &env->cp15.vtcr_el2;
>      }
>      return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
>  }

thanks
-- PMM



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