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Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless |
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Date: |
Tue, 8 Sep 2015 08:20:59 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 |
On 09/08/2015 01:19 AM, Peter Maydell wrote:
> The tcg common code isn't smart enough to notice it only
> needs to calculate not(t1) once ?
Correct, we do no value numbering or cse.
> In the overwhelmingly common case (x86 tcg backend)
> we would save an insn every time, right?
Yes. It all depends on what value is used for NZCV, of course.
Thankfully we *do* do dead code elimination, which is why I unconditionally
compute both T1 and T2, and let them be deleted should they be unused.
> I wouldn't bother to make the front-end generate different
> code for the backend does/doesn't have andc situations,
> certainly.
I'll mock it up and see how much duplication there is. And also check it out
on a Haswell host, which does have andc.
r~
- Re: [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare, (continued)
[Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/02