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[Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using inte
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state |
Date: |
Tue, 8 Sep 2015 17:51:13 +0100 |
Change the implementation of the Interrupt Control and State Register
in the v7M NVIC to not use the running_irq and last_active internal
state fields in the GIC. These fields don't correspond to state in
a real GIC and will be removed soon.
The changes to the ICSR are:
* the VECTACTIVE field is documented as identical to the IPSR[8:0]
field, so implement it that way
* implement RETTOBASE via looking at the active state bits
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index e13b729..3ec8408 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -185,26 +185,25 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
return cpu->midr;
case 0xd04: /* Interrupt Control State. */
/* VECTACTIVE */
- val = s->gic.running_irq[0];
+ cpu = ARM_CPU(current_cpu);
+ val = cpu->env.v7m.exception;
if (val == 1023) {
val = 0;
} else if (val >= 32) {
val -= 16;
}
- /* RETTOBASE */
- if (s->gic.running_irq[0] == 1023
- || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
- val |= (1 << 11);
- }
/* VECTPENDING */
if (s->gic.current_pending[0] != 1023)
val |= (s->gic.current_pending[0] << 12);
- /* ISRPENDING */
+ /* ISRPENDING and RETTOBASE */
for (irq = 32; irq < s->num_irq; irq++) {
if (s->gic.irq_state[irq].pending) {
val |= (1 << 22);
break;
}
+ if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active)
{
+ val |= (1 << 11);
+ }
}
/* PENDSTSET */
if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
--
1.9.1
- [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort, (continued)
- [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state,
Peter Maydell <=
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers, Peter Maydell, 2015/09/08
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/09/08