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[Qemu-devel] [PATCH v2 1/2] update Linux headers to 4.2


From: Paolo Bonzini
Subject: [Qemu-devel] [PATCH v2 1/2] update Linux headers to 4.2
Date: Wed, 9 Sep 2015 18:34:00 +0200

Signed-off-by: Paolo Bonzini <address@hidden>
---
 hw/pci/pcie_aer.c                            |   4 +-
 include/standard-headers/linux/pci_regs.h    | 381 ++++++++++++++++++++-------
 include/standard-headers/linux/virtio_ring.h |   3 +-
 linux-headers/asm-x86/hyperv.h               |   2 +
 linux-headers/asm-x86/kvm.h                  |   4 +-
 scripts/update-linux-headers.sh              |   1 +
 6 files changed, 294 insertions(+), 101 deletions(-)

diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index f1847ac..8e4bd56 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -827,8 +827,8 @@ typedef struct PCIEAERErrorName {
  */
 static const struct PCIEAERErrorName pcie_aer_error_list[] = {
     {
-        .name = "TRAIN",
-        .val = PCI_ERR_UNC_TRAIN,
+        .name = "UND",
+        .val = PCI_ERR_UNC_UND,
         .correctable = false,
     }, {
         .name = "DLP",
diff --git a/include/standard-headers/linux/pci_regs.h 
b/include/standard-headers/linux/pci_regs.h
index 57e8c80..413417f 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -13,10 +13,10 @@
  *     PCI to PCI Bridge Specification
  *     PCI System Design Guide
  *
- *     For hypertransport information, please consult the following manuals
- *     from http://www.hypertransport.org
+ *     For HyperTransport information, please consult the following manuals
+ *     from http://www.hypertransport.org
  *
- *     The Hypertransport I/O Link Specification
+ *     The HyperTransport I/O Link Specification
  */
 
 #ifndef LINUX_PCI_REGS_H
@@ -26,6 +26,7 @@
  * Under PCI, each device has 256 bytes of configuration address space,
  * of which the first 64 bytes are standardized as follows:
  */
+#define PCI_STD_HEADER_SIZEOF  64
 #define PCI_VENDOR_ID          0x00    /* 16 bits */
 #define PCI_DEVICE_ID          0x02    /* 16 bits */
 #define PCI_COMMAND            0x04    /* 16 bits */
@@ -36,7 +37,7 @@
 #define  PCI_COMMAND_INVALIDATE        0x10    /* Use memory write and 
invalidate */
 #define  PCI_COMMAND_VGA_PALETTE 0x20  /* Enable palette snooping */
 #define  PCI_COMMAND_PARITY    0x40    /* Enable parity checking */
-#define  PCI_COMMAND_WAIT      0x80    /* Enable address/data stepping */
+#define  PCI_COMMAND_WAIT      0x80    /* Enable address/data stepping */
 #define  PCI_COMMAND_SERR      0x100   /* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK 0x200   /* Enable back-to-back writes */
 #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
@@ -44,7 +45,7 @@
 #define PCI_STATUS             0x06    /* 16 bits */
 #define  PCI_STATUS_INTERRUPT  0x08    /* Interrupt status */
 #define  PCI_STATUS_CAP_LIST   0x10    /* Support Capability List */
-#define  PCI_STATUS_66MHZ      0x20    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_66MHZ      0x20    /* Support 66 MHz PCI 2.1 bus */
 #define  PCI_STATUS_UDF                0x40    /* Support User Definable 
Features [obsolete] */
 #define  PCI_STATUS_FAST_BACK  0x80    /* Accept fast-back to back */
 #define  PCI_STATUS_PARITY     0x100   /* Detected parity error */
@@ -125,7 +126,8 @@
 #define  PCI_IO_RANGE_TYPE_MASK        0x0fUL  /* I/O bridging type */
 #define  PCI_IO_RANGE_TYPE_16  0x00
 #define  PCI_IO_RANGE_TYPE_32  0x01
-#define  PCI_IO_RANGE_MASK     (~0x0fUL)
+#define  PCI_IO_RANGE_MASK     (~0x0fUL) /* Standard 4K I/O windows */
+#define  PCI_IO_1K_RANGE_MASK  (~0x03UL) /* Intel 1K I/O windows */
 #define PCI_SEC_STATUS         0x1e    /* Secondary status register, only bit 
14 used */
 #define PCI_MEMORY_BASE                0x20    /* Memory range behind */
 #define PCI_MEMORY_LIMIT       0x22
@@ -203,16 +205,18 @@
 #define  PCI_CAP_ID_CHSWP      0x06    /* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX       0x07    /* PCI-X */
 #define  PCI_CAP_ID_HT         0x08    /* HyperTransport */
-#define  PCI_CAP_ID_VNDR       0x09    /* Vendor specific */
+#define  PCI_CAP_ID_VNDR       0x09    /* Vendor-Specific */
 #define  PCI_CAP_ID_DBG                0x0A    /* Debug port */
 #define  PCI_CAP_ID_CCRC       0x0B    /* CompactPCI Central Resource Control 
*/
-#define  PCI_CAP_ID_SHPC       0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_SHPC       0x0C    /* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_SSVID      0x0D    /* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3       0x0E    /* AGP Target PCI-PCI bridge */
-#define  PCI_CAP_ID_EXP        0x10    /* PCI Express */
+#define  PCI_CAP_ID_SECDEV     0x0F    /* Secure Device */
+#define  PCI_CAP_ID_EXP                0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX       0x11    /* MSI-X */
-#define  PCI_CAP_ID_SATA       0x12    /* Serial ATA */
+#define  PCI_CAP_ID_SATA       0x12    /* SATA Data/Index Conf. */
 #define  PCI_CAP_ID_AF         0x13    /* PCI Advanced Features */
+#define  PCI_CAP_ID_MAX                PCI_CAP_ID_AF
 #define PCI_CAP_LIST_NEXT      1       /* Next capability in the list */
 #define PCI_CAP_FLAGS          2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF         4
@@ -264,8 +268,8 @@
 #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of 
requests */
 #define  PCI_AGP_COMMAND_SBA   0x0200  /* Sideband addressing enabled */
 #define  PCI_AGP_COMMAND_AGP   0x0100  /* Allow processing of AGP transactions 
*/
-#define  PCI_AGP_COMMAND_64BIT 0x0020  /* Allow processing of 64-bit addresses 
*/
-#define  PCI_AGP_COMMAND_FW    0x0010  /* Force FW transfers */
+#define  PCI_AGP_COMMAND_64BIT 0x0020  /* Allow processing of 64-bit addresses 
*/
+#define  PCI_AGP_COMMAND_FW    0x0010  /* Force FW transfers */
 #define  PCI_AGP_COMMAND_RATE4 0x0004  /* Use 4x rate */
 #define  PCI_AGP_COMMAND_RATE2 0x0002  /* Use 2x rate */
 #define  PCI_AGP_COMMAND_RATE1 0x0001  /* Use 1x rate */
@@ -277,6 +281,7 @@
 #define  PCI_VPD_ADDR_MASK     0x7fff  /* Address mask */
 #define  PCI_VPD_ADDR_F                0x8000  /* Write 0, 1 indicates 
completion */
 #define PCI_VPD_DATA           4       /* 32-bits of data returned here */
+#define PCI_CAP_VPD_SIZEOF     8
 
 /* Slot Identification */
 
@@ -287,32 +292,37 @@
 
 /* Message Signalled Interrupts registers */
 
-#define PCI_MSI_FLAGS          2       /* Various flags */
-#define  PCI_MSI_FLAGS_64BIT   0x80    /* 64-bit addresses allowed */
-#define  PCI_MSI_FLAGS_QSIZE   0x70    /* Message queue size configured */
-#define  PCI_MSI_FLAGS_QMASK   0x0e    /* Maximum queue size available */
-#define  PCI_MSI_FLAGS_ENABLE  0x01    /* MSI feature enabled */
-#define  PCI_MSI_FLAGS_MASKBIT 0x100   /* 64-bit mask bits allowed */
+#define PCI_MSI_FLAGS          2       /* Message Control */
+#define  PCI_MSI_FLAGS_ENABLE  0x0001  /* MSI feature enabled */
+#define  PCI_MSI_FLAGS_QMASK   0x000e  /* Maximum queue size available */
+#define  PCI_MSI_FLAGS_QSIZE   0x0070  /* Message queue size configured */
+#define  PCI_MSI_FLAGS_64BIT   0x0080  /* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_MASKBIT 0x0100  /* Per-vector masking capable */
 #define PCI_MSI_RFU            3       /* Rest of capability flags */
 #define PCI_MSI_ADDRESS_LO     4       /* Lower 32 bits */
 #define PCI_MSI_ADDRESS_HI     8       /* Upper 32 bits (if 
PCI_MSI_FLAGS_64BIT set) */
 #define PCI_MSI_DATA_32                8       /* 16 bits of data for 32-bit 
devices */
 #define PCI_MSI_MASK_32                12      /* Mask bits register for 
32-bit devices */
-#define PCI_MSI_PENDING_32     16      /* Pending bits register for 32-bit 
devices */
+#define PCI_MSI_PENDING_32     16      /* Pending intrs for 32-bit devices */
 #define PCI_MSI_DATA_64                12      /* 16 bits of data for 64-bit 
devices */
 #define PCI_MSI_MASK_64                16      /* Mask bits register for 
64-bit devices */
-#define PCI_MSI_PENDING_64     20      /* Pending bits register for 32-bit 
devices */
+#define PCI_MSI_PENDING_64     20      /* Pending intrs for 64-bit devices */
 
 /* MSI-X registers */
-#define PCI_MSIX_FLAGS         2
-#define  PCI_MSIX_FLAGS_QSIZE  0x7FF
-#define  PCI_MSIX_FLAGS_ENABLE (1 << 15)
-#define  PCI_MSIX_FLAGS_MASKALL        (1 << 14)
-#define PCI_MSIX_TABLE         4
-#define PCI_MSIX_PBA           8
-#define  PCI_MSIX_FLAGS_BIRMASK        (7 << 0)
-
-/* MSI-X entry's format */
+#define PCI_MSIX_FLAGS         2       /* Message Control */
+#define  PCI_MSIX_FLAGS_QSIZE  0x07FF  /* Table size */
+#define  PCI_MSIX_FLAGS_MASKALL        0x4000  /* Mask all vectors for this 
function */
+#define  PCI_MSIX_FLAGS_ENABLE 0x8000  /* MSI-X enable */
+#define PCI_MSIX_TABLE         4       /* Table offset */
+#define  PCI_MSIX_TABLE_BIR    0x00000007 /* BAR index */
+#define  PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */
+#define PCI_MSIX_PBA           8       /* Pending Bit Array offset */
+#define  PCI_MSIX_PBA_BIR      0x00000007 /* BAR index */
+#define  PCI_MSIX_PBA_OFFSET   0xfffffff8 /* Offset into specified BAR */
+#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
+#define PCI_CAP_MSIX_SIZEOF    12      /* size of MSIX registers */
+
+/* MSI-X Table entry format */
 #define PCI_MSIX_ENTRY_SIZE            16
 #define  PCI_MSIX_ENTRY_LOWER_ADDR     0
 #define  PCI_MSIX_ENTRY_UPPER_ADDR     4
@@ -341,8 +351,9 @@
 #define  PCI_AF_CTRL_FLR       0x01
 #define PCI_AF_STATUS          5
 #define  PCI_AF_STATUS_TP      0x01
+#define PCI_CAP_AF_SIZEOF      6       /* size of AF registers */
 
-/* PCI-X registers */
+/* PCI-X registers (Type 0 (non-bridge) devices) */
 
 #define PCI_X_CMD              2       /* Modes & Features */
 #define  PCI_X_CMD_DPERR_E     0x0001  /* Data Parity Error Recovery Enable */
@@ -362,7 +373,7 @@
 #define  PCI_X_CMD_SPLIT_16    0x0060  /* Max 16 */
 #define  PCI_X_CMD_SPLIT_32    0x0070  /* Max 32 */
 #define  PCI_X_CMD_MAX_SPLIT   0x0070  /* Max Outstanding Split Transactions */
-#define  PCI_X_CMD_VERSION(x)  (((x) >> 12) & 3) /* Version */
+#define  PCI_X_CMD_VERSION(x)  (((x) >> 12) & 3) /* Version */
 #define PCI_X_STATUS           4       /* PCI-X capabilities */
 #define  PCI_X_STATUS_DEVFN    0x000000ff      /* A copy of devfn */
 #define  PCI_X_STATUS_BUS      0x0000ff00      /* A copy of bus nr */
@@ -377,11 +388,28 @@
 #define  PCI_X_STATUS_SPL_ERR  0x20000000      /* Rcvd Split Completion Error 
Msg */
 #define  PCI_X_STATUS_266MHZ   0x40000000      /* 266 MHz capable */
 #define  PCI_X_STATUS_533MHZ   0x80000000      /* 533 MHz capable */
+#define PCI_X_ECC_CSR          8       /* ECC control and status */
+#define PCI_CAP_PCIX_SIZEOF_V0 8       /* size of registers for Version 0 */
+#define PCI_CAP_PCIX_SIZEOF_V1 24      /* size for Version 1 */
+#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1  /* Same for v2 */
+
+/* PCI-X registers (Type 1 (bridge) devices) */
+
+#define PCI_X_BRIDGE_SSTATUS   2       /* Secondary Status */
+#define  PCI_X_SSTATUS_64BIT   0x0001  /* Secondary AD interface is 64 bits */
+#define  PCI_X_SSTATUS_133MHZ  0x0002  /* 133 MHz capable */
+#define  PCI_X_SSTATUS_FREQ    0x03c0  /* Secondary Bus Mode and Frequency */
+#define  PCI_X_SSTATUS_VERS    0x3000  /* PCI-X Capability Version */
+#define  PCI_X_SSTATUS_V1      0x1000  /* Mode 2, not Mode 1 */
+#define  PCI_X_SSTATUS_V2      0x2000  /* Mode 1 or Modes 1 and 2 */
+#define  PCI_X_SSTATUS_266MHZ  0x4000  /* 266 MHz capable */
+#define  PCI_X_SSTATUS_533MHZ  0x8000  /* 533 MHz capable */
+#define PCI_X_BRIDGE_STATUS    4       /* Bridge Status */
 
 /* PCI Bridge Subsystem ID registers */
 
-#define PCI_SSVID_VENDOR_ID     4      /* PCI-Bridge subsystem vendor id 
register */
-#define PCI_SSVID_DEVICE_ID     6      /* PCI-Bridge subsystem device id 
register */
+#define PCI_SSVID_VENDOR_ID     4      /* PCI Bridge subsystem vendor ID */
+#define PCI_SSVID_DEVICE_ID     6      /* PCI Bridge subsystem device ID */
 
 /* PCI Express capability registers */
 
@@ -393,24 +421,24 @@
 #define  PCI_EXP_TYPE_ROOT_PORT 0x4    /* Root Port */
 #define  PCI_EXP_TYPE_UPSTREAM 0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6   /* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7   /* PCI/PCI-X Bridge */
-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7   /* PCIe to PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8  /* PCI/PCI-X to PCIe Bridge */
 #define  PCI_EXP_TYPE_RC_END   0x9     /* Root Complex Integrated Endpoint */
-#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
+#define  PCI_EXP_TYPE_RC_EC    0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT     0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ      0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP         4       /* Device capabilities */
-#define  PCI_EXP_DEVCAP_PAYLOAD        0x07    /* Max_Payload_Size */
-#define  PCI_EXP_DEVCAP_PHANTOM        0x18    /* Phantom functions */
-#define  PCI_EXP_DEVCAP_EXT_TAG        0x20    /* Extended tags */
-#define  PCI_EXP_DEVCAP_L0S    0x1c0   /* L0s Acceptable Latency */
-#define  PCI_EXP_DEVCAP_L1     0xe00   /* L1 Acceptable Latency */
-#define  PCI_EXP_DEVCAP_ATN_BUT        0x1000  /* Attention Button Present */
-#define  PCI_EXP_DEVCAP_ATN_IND        0x2000  /* Attention Indicator Present 
*/
-#define  PCI_EXP_DEVCAP_PWR_IND        0x4000  /* Power Indicator Present */
-#define  PCI_EXP_DEVCAP_RBER   0x8000  /* Role-Based Error Reporting */
-#define  PCI_EXP_DEVCAP_PWR_VAL        0x3fc0000 /* Slot Power Limit Value */
-#define  PCI_EXP_DEVCAP_PWR_SCL        0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_PAYLOAD        0x00000007 /* Max_Payload_Size */
+#define  PCI_EXP_DEVCAP_PHANTOM        0x00000018 /* Phantom functions */
+#define  PCI_EXP_DEVCAP_EXT_TAG        0x00000020 /* Extended tags */
+#define  PCI_EXP_DEVCAP_L0S    0x000001c0 /* L0s Acceptable Latency */
+#define  PCI_EXP_DEVCAP_L1     0x00000e00 /* L1 Acceptable Latency */
+#define  PCI_EXP_DEVCAP_ATN_BUT        0x00001000 /* Attention Button Present 
*/
+#define  PCI_EXP_DEVCAP_ATN_IND        0x00002000 /* Attention Indicator 
Present */
+#define  PCI_EXP_DEVCAP_PWR_IND        0x00004000 /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBER   0x00008000 /* Role-Based Error Reporting */
+#define  PCI_EXP_DEVCAP_PWR_VAL        0x03fc0000 /* Slot Power Limit Value */
+#define  PCI_EXP_DEVCAP_PWR_SCL        0x0c000000 /* Slot Power Limit Scale */
 #define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL         8       /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE   0x0001  /* Correctable Error Reporting En. */
@@ -424,47 +452,61 @@
 #define  PCI_EXP_DEVCTL_AUX_PME        0x0400  /* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ 0x7000  /* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_READRQ_128B  0x0000 /* 128 Bytes */
+#define  PCI_EXP_DEVCTL_READRQ_256B  0x1000 /* 256 Bytes */
+#define  PCI_EXP_DEVCTL_READRQ_512B  0x2000 /* 512 Bytes */
+#define  PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
 #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA         10      /* Device Status */
-#define  PCI_EXP_DEVSTA_CED    0x01    /* Correctable Error Detected */
-#define  PCI_EXP_DEVSTA_NFED   0x02    /* Non-Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_FED    0x04    /* Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_URD    0x08    /* Unsupported Request Detected */
-#define  PCI_EXP_DEVSTA_AUXPD  0x10    /* AUX Power Detected */
-#define  PCI_EXP_DEVSTA_TRPND  0x20    /* Transactions Pending */
+#define  PCI_EXP_DEVSTA_CED    0x0001  /* Correctable Error Detected */
+#define  PCI_EXP_DEVSTA_NFED   0x0002  /* Non-Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_FED    0x0004  /* Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_URD    0x0008  /* Unsupported Request Detected */
+#define  PCI_EXP_DEVSTA_AUXPD  0x0010  /* AUX Power Detected */
+#define  PCI_EXP_DEVSTA_TRPND  0x0020  /* Transactions Pending */
 #define PCI_EXP_LNKCAP         12      /* Link Capabilities */
 #define  PCI_EXP_LNKCAP_SLS    0x0000000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
+#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 #define  PCI_EXP_LNKCAP_MLW    0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS  0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL  0x00007000 /* L0s Exit Latency */
 #define  PCI_EXP_LNKCAP_L1EL   0x00038000 /* L1 Exit Latency */
-#define  PCI_EXP_LNKCAP_CLKPM  0x00040000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_CLKPM  0x00040000 /* Clock Power Management */
 #define  PCI_EXP_LNKCAP_SDERC  0x00080000 /* Surprise Down Error Reporting 
Capable */
 #define  PCI_EXP_LNKCAP_DLLLARC        0x00100000 /* Data Link Layer Link 
Active Reporting Capable */
 #define  PCI_EXP_LNKCAP_LBNC   0x00200000 /* Link Bandwidth Notification 
Capability */
 #define  PCI_EXP_LNKCAP_PN     0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL         16      /* Link Control */
 #define  PCI_EXP_LNKCTL_ASPMC  0x0003  /* ASPM Control */
+#define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001        /* L0s Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L1  0x0002        /* L1 Enable */
 #define  PCI_EXP_LNKCTL_RCB    0x0008  /* Read Completion Boundary */
 #define  PCI_EXP_LNKCTL_LD     0x0010  /* Link Disable */
 #define  PCI_EXP_LNKCTL_RL     0x0020  /* Retrain Link */
 #define  PCI_EXP_LNKCTL_CCC    0x0040  /* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_ES     0x0080  /* Extended Synch */
-#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100        /* Enable clkreq */
+#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
 #define  PCI_EXP_LNKCTL_HAWD   0x0200  /* Hardware Autonomous Width Disable */
 #define  PCI_EXP_LNKCTL_LBMIE  0x0400  /* Link Bandwidth Management Interrupt 
Enable */
-#define  PCI_EXP_LNKCTL_LABIE  0x0800  /* Lnk Autonomous Bandwidth Interrupt 
Enable */
+#define  PCI_EXP_LNKCTL_LABIE  0x0800  /* Link Autonomous Bandwidth Interrupt 
Enable */
 #define PCI_EXP_LNKSTA         18      /* Link Status */
 #define  PCI_EXP_LNKSTA_CLS    0x000f  /* Current Link Speed */
-#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
-#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
-#define  PCI_EXP_LNKSTA_NLW    0x03f0  /* Nogotiated Link Width */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKSTA_NLW    0x03f0  /* Negotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_X1 0x0010  /* Current Link Width x1 */
+#define  PCI_EXP_LNKSTA_NLW_X2 0x0020  /* Current Link Width x2 */
+#define  PCI_EXP_LNKSTA_NLW_X4 0x0040  /* Current Link Width x4 */
+#define  PCI_EXP_LNKSTA_NLW_X8 0x0080  /* Current Link Width x8 */
 #define  PCI_EXP_LNKSTA_NLW_SHIFT 4    /* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_LT     0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SLC    0x1000  /* Slot Clock Configuration */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */
 #define  PCI_EXP_LNKSTA_LBMS   0x4000  /* Link Bandwidth Management Status */
 #define  PCI_EXP_LNKSTA_LABS   0x8000  /* Link Autonomous Bandwidth Status */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20      /* v1 endpoints end here */
 #define PCI_EXP_SLTCAP         20      /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_ABP    0x00000001 /* Attention Button Present */
 #define  PCI_EXP_SLTCAP_PCP    0x00000002 /* Power Controller Present */
@@ -486,8 +528,16 @@
 #define  PCI_EXP_SLTCTL_CCIE   0x0010  /* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE   0x0020  /* Hot-Plug Interrupt Enable */
 #define  PCI_EXP_SLTCTL_AIC    0x00c0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
+#define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking 
*/
+#define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
 #define  PCI_EXP_SLTCTL_PIC    0x0300  /* Power Indicator Control */
+#define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
+#define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
+#define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
 #define  PCI_EXP_SLTCTL_PCC    0x0400  /* Power Controller Control */
+#define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
+#define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
 #define  PCI_EXP_SLTCTL_EIC    0x0800  /* Electromechanical Interlock Control 
*/
 #define  PCI_EXP_SLTCTL_DLLSCE 0x1000  /* Data Link Layer State Changed Enable 
*/
 #define PCI_EXP_SLTSTA         26      /* Slot Status */
@@ -501,52 +551,94 @@
 #define  PCI_EXP_SLTSTA_EIS    0x0080  /* Electromechanical Interlock Status */
 #define  PCI_EXP_SLTSTA_DLLSC  0x0100  /* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL          28      /* Root Control */
-#define  PCI_EXP_RTCTL_SECEE   0x01    /* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE  0x02    /* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE   0x04    /* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE   0x08    /* PME Interrupt Enable */
-#define  PCI_EXP_RTCTL_CRSSVE  0x10    /* CRS Software Visibility Enable */
+#define  PCI_EXP_RTCTL_SECEE   0x0001  /* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE  0x0002  /* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE   0x0004  /* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE   0x0008  /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSSVE  0x0010  /* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP          30      /* Root Capabilities */
+#define  PCI_EXP_RTCAP_CRSVIS  0x0001  /* CRS Software Visibility capability */
 #define PCI_EXP_RTSTA          32      /* Root Status */
-#define PCI_EXP_RTSTA_PME      0x10000 /* PME status */
-#define PCI_EXP_RTSTA_PENDING  0x20000 /* PME pending */
+#define PCI_EXP_RTSTA_PME      0x00010000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING  0x00020000 /* PME pending */
+/*
+ * The Device Capabilities 2, Device Status 2, Device Control 2,
+ * Link Capabilities 2, Link Status 2, Link Control 2,
+ * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
+ * are only present on devices with PCIe Capability version 2.
+ * Use pcie_capability_read_word() and similar interfaces to use them
+ * safely.
+ */
 #define PCI_EXP_DEVCAP2                36      /* Device Capabilities 2 */
-#define  PCI_EXP_DEVCAP2_ARI   0x20    /* Alternative Routing-ID */
-#define  PCI_EXP_DEVCAP2_LTR   0x800   /* Latency tolerance reporting */
-#define  PCI_EXP_OBFF_MASK     0xc0000 /* OBFF support mechanism */
-#define  PCI_EXP_OBFF_MSG      0x40000 /* New message signaling */
-#define  PCI_EXP_OBFF_WAKE     0x80000 /* Re-use WAKE# for OBFF */
+#define  PCI_EXP_DEVCAP2_ARI           0x00000020 /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR           0x00000800 /* Latency tolerance 
reporting */
+#define  PCI_EXP_DEVCAP2_OBFF_MASK     0x000c0000 /* OBFF support mechanism */
+#define  PCI_EXP_DEVCAP2_OBFF_MSG      0x00040000 /* New message signaling */
+#define  PCI_EXP_DEVCAP2_OBFF_WAKE     0x00080000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2                40      /* Device Control 2 */
-#define  PCI_EXP_DEVCTL2_ARI   0x20    /* Alternative Routing-ID */
-#define  PCI_EXP_IDO_REQ_EN    0x100   /* ID-based ordering request enable */
-#define  PCI_EXP_IDO_CMP_EN    0x200   /* ID-based ordering completion enable 
*/
-#define  PCI_EXP_LTR_EN                0x400   /* Latency tolerance reporting 
*/
-#define  PCI_EXP_OBFF_MSGA_EN  0x2000  /* OBFF enable with Message type A */
-#define  PCI_EXP_OBFF_MSGB_EN  0x4000  /* OBFF enable with Message type B */
-#define  PCI_EXP_OBFF_WAKE_EN  0x6000  /* OBFF using WAKE# signaling */
+#define  PCI_EXP_DEVCTL2_COMP_TIMEOUT  0x000f  /* Completion Timeout Value */
+#define  PCI_EXP_DEVCTL2_ARI           0x0020  /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCTL2_IDO_REQ_EN    0x0100  /* Allow IDO for requests */
+#define  PCI_EXP_DEVCTL2_IDO_CMP_EN    0x0200  /* Allow IDO for completions */
+#define  PCI_EXP_DEVCTL2_LTR_EN                0x0400  /* Enable LTR mechanism 
*/
+#define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN  0x2000  /* Enable OBFF Message type A */
+#define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN  0x4000  /* Enable OBFF Message type B */
+#define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN  0x6000  /* OBFF using WAKE# signaling */
+#define PCI_EXP_DEVSTA2                42      /* Device Status 2 */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44      /* v2 endpoints end here */
+#define PCI_EXP_LNKCAP2                44      /* Link Capabilities 2 */
+#define  PCI_EXP_LNKCAP2_SLS_2_5GB     0x00000002 /* Supported Speed 2.5GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_5_0GB     0x00000004 /* Supported Speed 5.0GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_8_0GB     0x00000008 /* Supported Speed 8.0GT/s */
+#define  PCI_EXP_LNKCAP2_CROSSLINK     0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2                48      /* Link Control 2 */
+#define PCI_EXP_LNKSTA2                50      /* Link Status 2 */
+#define PCI_EXP_SLTCAP2                52      /* Slot Capabilities 2 */
 #define PCI_EXP_SLTCTL2                56      /* Slot Control 2 */
+#define PCI_EXP_SLTSTA2                58      /* Slot Status 2 */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)         (header & 0x0000ffff)
 #define PCI_EXT_CAP_VER(header)                ((header >> 16) & 0xf)
 #define PCI_EXT_CAP_NEXT(header)       ((header >> 20) & 0xffc)
 
-#define PCI_EXT_CAP_ID_ERR     1
-#define PCI_EXT_CAP_ID_VC      2
-#define PCI_EXT_CAP_ID_DSN     3
-#define PCI_EXT_CAP_ID_PWR     4
-#define PCI_EXT_CAP_ID_VNDR    11
-#define PCI_EXT_CAP_ID_ACS     13
-#define PCI_EXT_CAP_ID_ARI     14
-#define PCI_EXT_CAP_ID_ATS     15
-#define PCI_EXT_CAP_ID_SRIOV   16
-#define PCI_EXT_CAP_ID_LTR     24
+#define PCI_EXT_CAP_ID_ERR     0x01    /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC      0x02    /* Virtual Channel Capability */
+#define PCI_EXT_CAP_ID_DSN     0x03    /* Device Serial Number */
+#define PCI_EXT_CAP_ID_PWR     0x04    /* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLD    0x05    /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILC   0x06    /* Root Complex Internal Link Control */
+#define PCI_EXT_CAP_ID_RCEC    0x07    /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC    0x08    /* Multi-Function VC Capability */
+#define PCI_EXT_CAP_ID_VC9     0x09    /* same as _VC */
+#define PCI_EXT_CAP_ID_RCRB    0x0A    /* Root Complex RB? */
+#define PCI_EXT_CAP_ID_VNDR    0x0B    /* Vendor-Specific */
+#define PCI_EXT_CAP_ID_CAC     0x0C    /* Config Access - obsolete */
+#define PCI_EXT_CAP_ID_ACS     0x0D    /* Access Control Services */
+#define PCI_EXT_CAP_ID_ARI     0x0E    /* Alternate Routing ID */
+#define PCI_EXT_CAP_ID_ATS     0x0F    /* Address Translation Services */
+#define PCI_EXT_CAP_ID_SRIOV   0x10    /* Single Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MRIOV   0x11    /* Multi Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MCAST   0x12    /* Multicast */
+#define PCI_EXT_CAP_ID_PRI     0x13    /* Page Request Interface */
+#define PCI_EXT_CAP_ID_AMD_XXX 0x14    /* Reserved for AMD */
+#define PCI_EXT_CAP_ID_REBAR   0x15    /* Resizable BAR */
+#define PCI_EXT_CAP_ID_DPA     0x16    /* Dynamic Power Allocation */
+#define PCI_EXT_CAP_ID_TPH     0x17    /* TPH Requester */
+#define PCI_EXT_CAP_ID_LTR     0x18    /* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_SECPCI  0x19    /* Secondary PCIe Capability */
+#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
+#define PCI_EXT_CAP_ID_PASID   0x1B    /* Process Address Space ID */
+#define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PASID
+
+#define PCI_EXT_CAP_DSN_SIZEOF 12
+#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS   4       /* Uncorrectable Error Status */
-#define  PCI_ERR_UNC_TRAIN     0x00000001      /* Training */
+#define  PCI_ERR_UNC_UND       0x00000001      /* Undefined */
 #define  PCI_ERR_UNC_DLP       0x00000010      /* Data Link Protocol */
+#define  PCI_ERR_UNC_SURPDN    0x00000020      /* Surprise Down */
 #define  PCI_ERR_UNC_POISON_TLP        0x00001000      /* Poisoned TLP */
 #define  PCI_ERR_UNC_FCP       0x00002000      /* Flow Control Protocol */
 #define  PCI_ERR_UNC_COMP_TIME 0x00004000      /* Completion Timeout */
@@ -556,6 +648,11 @@
 #define  PCI_ERR_UNC_MALF_TLP  0x00040000      /* Malformed TLP */
 #define  PCI_ERR_UNC_ECRC      0x00080000      /* ECRC Error Status */
 #define  PCI_ERR_UNC_UNSUP     0x00100000      /* Unsupported Request */
+#define  PCI_ERR_UNC_ACSV      0x00200000      /* ACS Violation */
+#define  PCI_ERR_UNC_INTN      0x00400000      /* internal error */
+#define  PCI_ERR_UNC_MCBTLP    0x00800000      /* MC blocked TLP */
+#define  PCI_ERR_UNC_ATOMEG    0x01000000      /* Atomic egress blocked */
+#define  PCI_ERR_UNC_TLPPRE    0x02000000      /* TLP prefix blocked */
 #define PCI_ERR_UNCOR_MASK     8       /* Uncorrectable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_UNCOR_SEVER    12      /* Uncorrectable Error Severity */
@@ -566,6 +663,9 @@
 #define  PCI_ERR_COR_BAD_DLLP  0x00000080      /* Bad DLLP Status */
 #define  PCI_ERR_COR_REP_ROLL  0x00000100      /* REPLAY_NUM Rollover */
 #define  PCI_ERR_COR_REP_TIMER 0x00001000      /* Replay Timer Timeout */
+#define  PCI_ERR_COR_ADV_NFAT  0x00002000      /* Advisory Non-Fatal */
+#define  PCI_ERR_COR_INTERNAL  0x00004000      /* Corrected Internal */
+#define  PCI_ERR_COR_LOG_OVER  0x00008000      /* Header Log Overflow */
 #define PCI_ERR_COR_MASK       20      /* Correctable Error Mask */
        /* Same bits as above */
 #define PCI_ERR_CAP            24      /* Advanced Error Capabilities */
@@ -586,9 +686,9 @@
 #define PCI_ERR_ROOT_COR_RCV           0x00000001      /* ERR_COR Received */
 /* Multi ERR_COR Received */
 #define PCI_ERR_ROOT_MULTI_COR_RCV     0x00000002
-/* ERR_FATAL/NONFATAL Recevied */
+/* ERR_FATAL/NONFATAL Received */
 #define PCI_ERR_ROOT_UNCOR_RCV         0x00000004
-/* Multi ERR_FATAL/NONFATAL Recevied */
+/* Multi ERR_FATAL/NONFATAL Received */
 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV   0x00000008
 #define PCI_ERR_ROOT_FIRST_FATAL       0x00000010      /* First Fatal */
 #define PCI_ERR_ROOT_NONFATAL_RCV      0x00000020      /* Non-Fatal Received */
@@ -596,13 +696,36 @@
 #define PCI_ERR_ROOT_ERR_SRC   52      /* Error Source Identification */
 
 /* Virtual Channel */
-#define PCI_VC_PORT_REG1       4
-#define PCI_VC_PORT_REG2       8
+#define PCI_VC_PORT_CAP1       4
+#define  PCI_VC_CAP1_EVCC      0x00000007      /* extended VC count */
+#define  PCI_VC_CAP1_LPEVCC    0x00000070      /* low prio extended VC count */
+#define  PCI_VC_CAP1_ARB_SIZE  0x00000c00
+#define PCI_VC_PORT_CAP2       8
+#define  PCI_VC_CAP2_32_PHASE          0x00000002
+#define  PCI_VC_CAP2_64_PHASE          0x00000004
+#define  PCI_VC_CAP2_128_PHASE         0x00000008
+#define  PCI_VC_CAP2_ARB_OFF           0xff000000
 #define PCI_VC_PORT_CTRL       12
+#define  PCI_VC_PORT_CTRL_LOAD_TABLE   0x00000001
 #define PCI_VC_PORT_STATUS     14
+#define  PCI_VC_PORT_STATUS_TABLE      0x00000001
 #define PCI_VC_RES_CAP         16
+#define  PCI_VC_RES_CAP_32_PHASE       0x00000002
+#define  PCI_VC_RES_CAP_64_PHASE       0x00000004
+#define  PCI_VC_RES_CAP_128_PHASE      0x00000008
+#define  PCI_VC_RES_CAP_128_PHASE_TB   0x00000010
+#define  PCI_VC_RES_CAP_256_PHASE      0x00000020
+#define  PCI_VC_RES_CAP_ARB_OFF                0xff000000
 #define PCI_VC_RES_CTRL                20
+#define  PCI_VC_RES_CTRL_LOAD_TABLE    0x00010000
+#define  PCI_VC_RES_CTRL_ARB_SELECT    0x000e0000
+#define  PCI_VC_RES_CTRL_ID            0x07000000
+#define  PCI_VC_RES_CTRL_ENABLE                0x80000000
 #define PCI_VC_RES_STATUS      26
+#define  PCI_VC_RES_STATUS_TABLE       0x00000001
+#define  PCI_VC_RES_STATUS_NEGO                0x00000002
+#define PCI_CAP_VC_BASE_SIZEOF         0x10
+#define PCI_CAP_VC_PER_VC_SIZEOF       0x0C
 
 /* Power Budgeting */
 #define PCI_PWR_DSR            4       /* Data Select Register */
@@ -615,9 +738,16 @@
 #define  PCI_PWR_DATA_RAIL(x)  (((x) >> 18) & 7)   /* Power Rail */
 #define PCI_PWR_CAP            12      /* Capability */
 #define  PCI_PWR_CAP_BUDGET(x) ((x) & 1)       /* Included in system budget */
+#define PCI_EXT_CAP_PWR_SIZEOF 16
+
+/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
+#define PCI_VNDR_HEADER                4       /* Vendor-Specific Header */
+#define  PCI_VNDR_HEADER_ID(x) ((x) & 0xffff)
+#define  PCI_VNDR_HEADER_REV(x)        (((x) >> 16) & 0xf)
+#define  PCI_VNDR_HEADER_LEN(x)        (((x) >> 20) & 0xfff)
 
 /*
- * Hypertransport sub capability types
+ * HyperTransport sub capability types
  *
  * Unfortunately there are both 3 bit and 5 bit capability types defined
  * in the HT spec, catering for that is a little messy. You probably don't
@@ -645,8 +775,10 @@
 #define HT_CAPTYPE_DIRECT_ROUTE        0xB0    /* Direct routing configuration 
*/
 #define HT_CAPTYPE_VCSET       0xB8    /* Virtual Channel configuration */
 #define HT_CAPTYPE_ERROR_RETRY 0xC0    /* Retry on error configuration */
-#define HT_CAPTYPE_GEN3                0xD0    /* Generation 3 hypertransport 
configuration */
-#define HT_CAPTYPE_PM          0xE0    /* Hypertransport powermanagement 
configuration */
+#define HT_CAPTYPE_GEN3                0xD0    /* Generation 3 HyperTransport 
configuration */
+#define HT_CAPTYPE_PM          0xE0    /* HyperTransport power management 
configuration */
+#define HT_CAP_SIZEOF_LONG     28      /* slave & primary */
+#define HT_CAP_SIZEOF_SHORT    24      /* host & secondary */
 
 /* Alternative Routing-ID Interpretation */
 #define PCI_ARI_CAP            0x04    /* ARI Capability Register */
@@ -657,6 +789,7 @@
 #define  PCI_ARI_CTRL_MFVC     0x0001  /* MFVC Function Groups Enable */
 #define  PCI_ARI_CTRL_ACS      0x0002  /* ACS Function Groups Enable */
 #define  PCI_ARI_CTRL_FG(x)    (((x) >> 4) & 7) /* Function Group */
+#define PCI_EXT_CAP_ARI_SIZEOF 8
 
 /* Address Translation Service */
 #define PCI_ATS_CAP            0x04    /* ATS Capability Register */
@@ -666,6 +799,29 @@
 #define  PCI_ATS_CTRL_ENABLE   0x8000  /* ATS Enable */
 #define  PCI_ATS_CTRL_STU(x)   ((x) & 0x1f)    /* Smallest Translation Unit */
 #define  PCI_ATS_MIN_STU       12      /* shift of minimum STU block */
+#define PCI_EXT_CAP_ATS_SIZEOF 8
+
+/* Page Request Interface */
+#define PCI_PRI_CTRL           0x04    /* PRI control register */
+#define  PCI_PRI_CTRL_ENABLE   0x01    /* Enable */
+#define  PCI_PRI_CTRL_RESET    0x02    /* Reset */
+#define PCI_PRI_STATUS         0x06    /* PRI status register */
+#define  PCI_PRI_STATUS_RF     0x001   /* Response Failure */
+#define  PCI_PRI_STATUS_UPRGI  0x002   /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_STOPPED        0x100   /* PRI Stopped */
+#define PCI_PRI_MAX_REQ                0x08    /* PRI max reqs supported */
+#define PCI_PRI_ALLOC_REQ      0x0c    /* PRI max reqs allowed */
+#define PCI_EXT_CAP_PRI_SIZEOF 16
+
+/* Process Address Space ID */
+#define PCI_PASID_CAP          0x04    /* PASID feature register */
+#define  PCI_PASID_CAP_EXEC    0x02    /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV    0x04    /* Privilege Mode Supported */
+#define PCI_PASID_CTRL         0x06    /* PASID control register */
+#define  PCI_PASID_CTRL_ENABLE 0x01    /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC   0x02    /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV   0x04    /* Privilege Mode Enable */
+#define PCI_EXT_CAP_PASID_SIZEOF       8
 
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP          0x04    /* SR-IOV Capabilities */
@@ -697,12 +853,14 @@
 #define  PCI_SRIOV_VFM_MI      0x1     /* Dormant.MigrateIn */
 #define  PCI_SRIOV_VFM_MO      0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV      0x3     /* Active.Available */
+#define PCI_EXT_CAP_SRIOV_SIZEOF 64
 
 #define PCI_LTR_MAX_SNOOP_LAT  0x4
 #define PCI_LTR_MAX_NOSNOOP_LAT        0x6
 #define  PCI_LTR_VALUE_MASK    0x000003ff
 #define  PCI_LTR_SCALE_MASK    0x00001c00
 #define  PCI_LTR_SCALE_SHIFT   10
+#define PCI_EXT_CAP_LTR_SIZEOF 8
 
 /* Access Control Service */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
@@ -713,7 +871,38 @@
 #define  PCI_ACS_UF            0x10    /* Upstream Forwarding */
 #define  PCI_ACS_EC            0x20    /* P2P Egress Control */
 #define  PCI_ACS_DT            0x40    /* Direct Translated P2P */
+#define PCI_ACS_EGRESS_BITS    0x05    /* ACS Egress Control Vector Size */
 #define PCI_ACS_CTRL           0x06    /* ACS Control Register */
 #define PCI_ACS_EGRESS_CTL_V   0x08    /* ACS Egress Control Vector */
 
+#define PCI_VSEC_HDR           4       /* extended cap - vendor-specific */
+#define  PCI_VSEC_HDR_LEN_SHIFT        20      /* shift for length field */
+
+/* SATA capability */
+#define PCI_SATA_REGS          4       /* SATA REGs specifier */
+#define  PCI_SATA_REGS_MASK    0xF     /* location - BAR#/inline */
+#define  PCI_SATA_REGS_INLINE  0xF     /* REGS in config space */
+#define PCI_SATA_SIZEOF_SHORT  8
+#define PCI_SATA_SIZEOF_LONG   16
+
+/* Resizable BARs */
+#define PCI_REBAR_CTRL         8       /* control register */
+#define  PCI_REBAR_CTRL_NBAR_MASK      (7 << 5)        /* mask for # bars */
+#define  PCI_REBAR_CTRL_NBAR_SHIFT     5       /* shift for # bars */
+
+/* Dynamic Power Allocation */
+#define PCI_DPA_CAP            4       /* capability register */
+#define  PCI_DPA_CAP_SUBSTATE_MASK     0x1F    /* # substates - 1 */
+#define PCI_DPA_BASE_SIZEOF    16      /* size with 0 substates */
+
+/* TPH Requester */
+#define PCI_TPH_CAP            4       /* capability register */
+#define  PCI_TPH_CAP_LOC_MASK  0x600   /* location mask */
+#define   PCI_TPH_LOC_NONE     0x000   /* no location */
+#define   PCI_TPH_LOC_CAP      0x200   /* in capability */
+#define   PCI_TPH_LOC_MSIX     0x400   /* in MSI-X */
+#define PCI_TPH_CAP_ST_MASK    0x07FF0000      /* st table mask */
+#define PCI_TPH_CAP_ST_SHIFT   16      /* st table shift */
+#define PCI_TPH_BASE_SIZEOF    12      /* size with no st table */
+
 #endif /* LINUX_PCI_REGS_H */
diff --git a/include/standard-headers/linux/virtio_ring.h 
b/include/standard-headers/linux/virtio_ring.h
index 6fe276f..023c6db 100644
--- a/include/standard-headers/linux/virtio_ring.h
+++ b/include/standard-headers/linux/virtio_ring.h
@@ -31,6 +31,7 @@
  * SUCH DAMAGE.
  *
  * Copyright Rusty Russell IBM Corporation 2007. */
+#include <stdint.h>
 #include "standard-headers/linux/types.h"
 #include "standard-headers/linux/virtio_types.h"
 
@@ -143,7 +144,7 @@ static inline void vring_init(struct vring *vr, unsigned 
int num, void *p,
        vr->num = num;
        vr->desc = p;
        vr->avail = p + num*sizeof(struct vring_desc);
-       vr->used = (void *)(((unsigned long)&vr->avail->ring[num] + 
sizeof(__virtio16)
+       vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] + 
sizeof(__virtio16)
                + align-1) & ~(align - 1));
 }
 
diff --git a/linux-headers/asm-x86/hyperv.h b/linux-headers/asm-x86/hyperv.h
index 8fba544..f36d56b 100644
--- a/linux-headers/asm-x86/hyperv.h
+++ b/linux-headers/asm-x86/hyperv.h
@@ -108,6 +108,8 @@
 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE          (1 << 4)
 /* Support for a virtual guest idle state is available */
 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE              (1 << 5)
+/* Guest crash data handler available */
+#define HV_X64_GUEST_CRASH_MSR_AVAILABLE               (1 << 10)
 
 /*
  * Implementation recommendations. Indicates which behaviors the hypervisor
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index a4ae82e..cd54147 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -354,7 +354,7 @@ struct kvm_xcrs {
 struct kvm_sync_regs {
 };
 
-#define KVM_QUIRK_LINT0_REENABLED      (1 << 0)
-#define KVM_QUIRK_CD_NW_CLEARED                (1 << 1)
+#define KVM_X86_QUIRK_LINT0_REENABLED  (1 << 0)
+#define KVM_X86_QUIRK_CD_NW_CLEARED    (1 << 1)
 
 #endif /* _ASM_X86_KVM_H */
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index f0e830c..7f7b592 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux-headers.sh
@@ -39,6 +39,7 @@ cp_virtio() {
             if
                 grep '#include' "$f" | grep -v -e 'linux/virtio' \
                                              -e 'linux/types' \
+                                             -e 'stdint' \
                                              -e 'linux/if_ether' \
                                              -e 'sys/' \
                                              > /dev/null
-- 
2.4.3





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