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Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from use


From: Bastian Koppelmann
Subject: Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode
Date: Sun, 13 Sep 2015 10:34:04 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0



On 09/06/2015 10:36 PM, Richard Henderson wrote:
On Sep 5, 2015 14:35, Bastian Koppelmann <address@hidden> wrote:
IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
the manual is fairly clear about that. User mode cpu ought not to read
these registers unconditionally.
When I last discussed this on the openrisc list, back in March, there was no 
real specification for user mode, and what bits are or should be accessible.

Looking at
   http://opencores.org/or1k/Architecture_Specification
today, that still seems to be the case.

In the meantime, dropping the privilege check makes linux-user GCC tests work 
better.

Looking at the article, user mode seems to be optional, so I'm not against it, but it does look weird. How does ork1sim do it?

Cheers,
Bastian



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