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[Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size |
Date: |
Mon, 14 Sep 2015 14:52:48 +0100 |
From: Nathan Rossi <address@hidden>
The GIC in ZynqMP cover a 64K address space, however the actual
registers are decoded within a 4K address space and mirrored at the 4K
boundaries. This change fixes the defined size for these regions as it
was set to 0x4000/16K incorrectly.
Signed-off-by: Nathan Rossi <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 97622ec..4005a99 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -46,7 +46,7 @@
* number of memory region aliases.
*/
-#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000
+#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
typedef struct XlnxZynqMPState {
--
1.9.1
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, (continued)
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size,
Peter Maydell <=
- [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 16/24] i.MX: Add GPIO devices to i.MX25 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 04/24] target-arm: Introduce DisasCompare, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 02/24] xlnx-zynqmp: Remove unnecessary brackets around error messages, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 18/24] target-arm: Add VTCR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 09/24] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Peter Maydell, 2015/09/14
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14