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[Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes with
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc |
Date: |
Mon, 14 Sep 2015 14:52:52 +0100 |
From: Richard Henderson <address@hidden>
Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator. The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 7d2e984..84a21ac 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -804,6 +804,14 @@ void arm_test_cc(DisasCompare *cmp, int cc)
tcg_gen_andc_i32(value, cpu_ZF, value);
break;
+ case 14: /* always */
+ case 15: /* always */
+ /* Use the ALWAYS condition, which will fold early.
+ * It doesn't matter what we use for the value. */
+ cond = TCG_COND_ALWAYS;
+ value = cpu_ZF;
+ goto no_invert;
+
default:
fprintf(stderr, "Bad condition code 0x%x\n", cc);
abort();
@@ -813,6 +821,7 @@ void arm_test_cc(DisasCompare *cmp, int cc)
cond = tcg_invert_cond(cond);
}
+ no_invert:
cmp->cond = cond;
cmp->value = value;
cmp->value_global = global;
--
1.9.1
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, (continued)
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc,
Peter Maydell <=
- [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 16/24] i.MX: Add GPIO devices to i.MX25 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 04/24] target-arm: Introduce DisasCompare, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 02/24] xlnx-zynqmp: Remove unnecessary brackets around error messages, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 18/24] target-arm: Add VTCR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 09/24] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Peter Maydell, 2015/09/14
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14