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[Qemu-devel] [PATCH v16 26/35] target-tilegx: Handle shift instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v16 26/35] target-tilegx: Handle shift instructions |
Date: |
Mon, 14 Sep 2015 15:43:33 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 56 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 54 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 9604320..c18e60c 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -470,6 +470,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
TCGv tdest = dest_gr(dc, dest);
TCGv tsrca = load_gr(dc, srca);
TCGv tsrcb = load_gr(dc, srcb);
+ TCGv t0;
const char *mnemonic;
switch (opext) {
@@ -662,7 +663,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
case OE_RRR(ROTL, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_rotl_tl(tdest, tsrca, tdest);
+ mnemonic = "rotl";
+ break;
case OE_RRR(SHL1ADDX, 0, X0):
case OE_RRR(SHL1ADDX, 0, X1):
case OE_RRR(SHL1ADDX, 7, Y0):
@@ -716,21 +720,45 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
break;
case OE_RRR(SHLX, 0, X0):
case OE_RRR(SHLX, 0, X1):
+ tcg_gen_andi_tl(tdest, tsrcb, 31);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlx";
+ break;
case OE_RRR(SHL, 0, X0):
case OE_RRR(SHL, 0, X1):
case OE_RRR(SHL, 6, Y0):
case OE_RRR(SHL, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ mnemonic = "shl";
+ break;
case OE_RRR(SHRS, 0, X0):
case OE_RRR(SHRS, 0, X1):
case OE_RRR(SHRS, 6, Y0):
case OE_RRR(SHRS, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_sar_tl(tdest, tsrca, tdest);
+ mnemonic = "shrs";
+ break;
case OE_RRR(SHRUX, 0, X0):
case OE_RRR(SHRUX, 0, X1):
+ t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, tsrcb, 31);
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shr_tl(tdest, tdest, t0);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ tcg_temp_free(t0);
+ mnemonic = "shrux";
+ break;
case OE_RRR(SHRU, 0, X0):
case OE_RRR(SHRU, 0, X1):
case OE_RRR(SHRU, 6, Y0):
case OE_RRR(SHRU, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shr_tl(tdest, tsrca, tdest);
+ mnemonic = "shru";
+ break;
case OE_RRR(SHUFFLEBYTES, 0, X0):
gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
mnemonic = "shufflebytes";
@@ -1064,22 +1092,46 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
unsigned opext,
case OE_SH(ROTLI, X1):
case OE_SH(ROTLI, Y0):
case OE_SH(ROTLI, Y1):
+ tcg_gen_rotli_tl(tdest, tsrca, imm);
+ mnemonic = "rotli";
+ break;
case OE_SH(SHLI, X0):
case OE_SH(SHLI, X1):
case OE_SH(SHLI, Y0):
case OE_SH(SHLI, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, imm);
+ mnemonic = "shli";
+ break;
case OE_SH(SHLXI, X0):
case OE_SH(SHLXI, X1):
+ tcg_gen_shli_tl(tdest, tsrca, imm & 31);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlxi";
+ break;
case OE_SH(SHRSI, X0):
case OE_SH(SHRSI, X1):
case OE_SH(SHRSI, Y0):
case OE_SH(SHRSI, Y1):
+ tcg_gen_sari_tl(tdest, tsrca, imm);
+ mnemonic = "shrsi";
+ break;
case OE_SH(SHRUI, X0):
case OE_SH(SHRUI, X1):
case OE_SH(SHRUI, Y0):
case OE_SH(SHRUI, Y1):
+ tcg_gen_shri_tl(tdest, tsrca, imm);
+ mnemonic = "shrui";
+ break;
case OE_SH(SHRUXI, X0):
case OE_SH(SHRUXI, X1):
+ if ((imm & 31) == 0) {
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ } else {
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shri_tl(tdest, tdest, imm & 31);
+ }
+ mnemonic = "shlxi";
+ break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
case OE_SH(V1SHRSI, X0):
--
2.4.3
- [Qemu-devel] [PATCH v16 18/35] target-tilegx: Handle most bit manipulation instructions, (continued)
- [Qemu-devel] [PATCH v16 18/35] target-tilegx: Handle most bit manipulation instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 11/35] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 19/35] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 20/35] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 22/35] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 23/35] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 21/35] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 25/35] target-tilegx: Handle bitfield instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 24/35] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 26/35] target-tilegx: Handle shift instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH v16 28/35] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 27/35] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 29/35] target-tilegx: Handle mask instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 30/35] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 34/35] target-tilegx: Handle v1shli, v1shrui, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 31/35] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 32/35] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 33/35] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 35/35] target-tilegx: Handle v1shl, v1shru, v1shrs, Richard Henderson, 2015/09/14