Re: [Qemu-devel] [PATCH RFC V4 0/4] Implement GIC-500 from GICv3 family for arm64

[Peter Maydell]

On 17 September 2015 at 19:54, Shlomo Pongratz <address@hidden> wrote:
> See inline.

(You don't need to keep saying this, by the way -- inline quoting and
response is the usual form of email on this list.)

> On Thursday, September 17, 2015, Peter Maydell <address@hidden>
> wrote:
>>
>> On 17 September 2015 at 19:18, Shlomo Pongratz <address@hidden>
>> wrote:
>> > The GICv3 spec limits the number of cores to 128.
>>
>> I don't believe it does (the only limit is the affinity fields
>> which have a limit up in the millions). Can you point me to the
>> part of the spec that you think imposes a lower limit?
>>
>
> I don't have the GICv3 spec at home only the GIC 500 which is based on it
> and is what implemented also in HW and it states:
>
> 1.1 About the GIC-500 The GIC-500 is a build-time configurable interrupt
> controller that supports up to 128 cores.

That's just a limit of a particular implementation, not of the
architecture.

> I'll send the GICv3 reference next week when I'll come back to work (I have
> it only at work).

Yes, that's the document which you need for architecture-level questions.

thanks
-- PMM