[Qemu-devel] [PATCH v2 06/22] target-arm: Add condexec state to insn_start

[Richard Henderson]

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
 target-arm/cpu.h           | 1 +
 target-arm/translate-a64.c | 2 +-
 target-arm/translate.c     | 3 ++-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1b80516..c4a7400 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -97,6 +97,7 @@
 struct arm_boot_info;
 
 #define NB_MMU_MODES 7
+#define TARGET_INSN_START_EXTRA_WORDS 1
 
 /* We currently assume float and double are IEEE single and double
    precision respectively.
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index c1efd30..1e16245 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11090,7 +11090,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
             tcg_ctx.gen_opc_instr_start[lj] = 1;
             tcg_ctx.gen_opc_icount[lj] = num_insns;
         }
-        tcg_gen_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc, 0);
         num_insns++;
 
         if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 555295e..982a3c1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11317,7 +11317,8 @@ static inline void 
gen_intermediate_code_internal(ARMCPU *cpu,
             tcg_ctx.gen_opc_instr_start[lj] = 1;
             tcg_ctx.gen_opc_icount[lj] = num_insns;
         }
-        tcg_gen_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc,
+                           (dc->condexec_cond << 4) | (dc->condexec_mask >> 
1));
         num_insns++;
 
 #ifdef CONFIG_USER_ONLY
-- 
2.1.0