[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 18/22] tcg: Add TCG_MAX_INSNS
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH v2 18/22] tcg: Add TCG_MAX_INSNS |
|
Date: |
Thu, 17 Sep 2015 21:55:25 -0700 |
Adjust all translators to respect it.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/translate.c | 3 +++
target-arm/translate-a64.c | 3 +++
target-arm/translate.c | 6 +++++-
target-cris/translate.c | 3 +++
target-i386/translate.c | 6 +++++-
target-lm32/translate.c | 3 +++
target-m68k/translate.c | 6 +++++-
target-microblaze/translate.c | 6 +++++-
target-mips/translate.c | 7 ++++++-
target-moxie/translate.c | 13 +++++++++++--
target-openrisc/translate.c | 3 +++
target-ppc/translate.c | 6 +++++-
target-s390x/translate.c | 3 +++
target-sh4/translate.c | 7 ++++++-
target-sparc/translate.c | 7 ++++++-
target-tilegx/translate.c | 3 +++
target-tricore/translate.c | 20 +++++++++++++-------
target-unicore32/translate.c | 3 +++
target-xtensa/translate.c | 3 +++
tcg/tcg.h | 1 +
20 files changed, 95 insertions(+), 17 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index c10193e..538e202 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2903,6 +2903,9 @@ static inline void
gen_intermediate_code_internal(AlphaCPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
if (in_superpage(&ctx, pc_start)) {
pc_mask = (1ULL << 41) - 1;
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 1e16245..c628490 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11072,6 +11072,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 982a3c1..7ddc28f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11258,8 +11258,12 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
lj = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 3d55a6a..d038bdb 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3155,6 +3155,9 @@ gen_intermediate_code_internal(CRISCPU *cpu,
TranslationBlock *tb,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
do {
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7501b91..d3282e8 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7932,8 +7932,12 @@ static inline void gen_intermediate_code_internal(X86CPU
*cpu,
lj = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
for(;;) {
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 8ea7929..e16c31a 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1069,6 +1069,9 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
do {
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index afef37f..185c565 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2991,8 +2991,12 @@ gen_intermediate_code_internal(M68kCPU *cpu,
TranslationBlock *tb,
lj = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
do {
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 1224456..58b27ca 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1674,8 +1674,12 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu,
TranslationBlock *tb,
lj = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
do
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1724756..b89ff81 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20198,8 +20198,13 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
MO_UNALN : MO_ALIGN;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index d71f55b..68588da 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -824,7 +824,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu,
TranslationBlock *tb,
target_ulong pc_start;
int j, lj = -1;
CPUMoxieState *env = &cpu->env;
- int num_insns;
+ int num_insns, max_insns;
pc_start = tb->pc;
ctx.pc = pc_start;
@@ -834,6 +834,13 @@ gen_intermediate_code_internal(MoxieCPU *cpu,
TranslationBlock *tb,
ctx.singlestep_enabled = 0;
ctx.bstate = BS_NONE;
num_insns = 0;
+ max_insns = tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
do {
@@ -862,10 +869,12 @@ gen_intermediate_code_internal(MoxieCPU *cpu,
TranslationBlock *tb,
ctx.opcode = cpu_lduw_code(env, ctx.pc);
ctx.pc += decode_opc(cpu, &ctx);
+ if (num_insns >= max_insns) {
+ break;
+ }
if (cs->singlestep_enabled) {
break;
}
-
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
break;
}
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 9755850..7573d34 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1654,6 +1654,9 @@ static inline void
gen_intermediate_code_internal(OpenRISCCPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fb1eb37..5ce79e0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11468,8 +11468,12 @@ static inline void
gen_intermediate_code_internal(PowerPCCPU *cpu,
#endif
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
tcg_clear_temp_count();
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 6bbc760..b1aa139 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5352,6 +5352,9 @@ static inline void gen_intermediate_code_internal(S390CPU
*cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index efaa6f6..b48b9bb 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1844,8 +1844,13 @@ gen_intermediate_code_internal(SuperHCPU *cpu,
TranslationBlock *tb,
ii = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+
gen_tb_start(tb);
while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) {
if (search_pc) {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6e5b82d..e6ecd21 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5236,8 +5236,13 @@ static inline void
gen_intermediate_code_internal(SPARCCPU *cpu,
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+
gen_tb_start(tb);
do {
if (spc) {
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index c23b761..a6b9cd8 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2081,6 +2081,9 @@ static inline void
gen_intermediate_code_internal(TileGXCPU *cpu,
if (cs->singlestep_enabled || singlestep) {
max_insns = 1;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
gen_tb_start(tb);
while (1) {
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index fa10d5c..5345486 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8274,13 +8274,24 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct
TranslationBlock *tb,
CPUTriCoreState *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
- int num_insns;
+ int num_insns, max_insns;
if (search_pc) {
qemu_log("search pc %d\n", search_pc);
}
num_insns = 0;
+ max_insns = tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (singlestep) {
+ max_insns = 1;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+
pc_start = tb->pc;
ctx.pc = pc_start;
ctx.saved_pc = -1;
@@ -8298,12 +8309,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct
TranslationBlock *tb,
ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0);
- if (tcg_op_buf_full()) {
- gen_save_pc(ctx.next_pc);
- tcg_gen_exit_tb(0);
- break;
- }
- if (singlestep) {
+ if (num_insns >= max_insns || tcg_op_buf_full()) {
gen_save_pc(ctx.next_pc);
tcg_gen_exit_tb(0);
break;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index cd23c4b..5e61e38 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1900,6 +1900,9 @@ static inline void
gen_intermediate_code_internal(UniCore32CPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
#ifndef CONFIG_USER_ONLY
if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index ea87cb5..4d4dc06 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -3014,6 +3014,9 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
dc.config = env->config;
dc.singlestep_enabled = cs->singlestep_enabled;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c975076..151e17d 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -194,6 +194,7 @@ typedef struct TCGPool {
#define TCG_POOL_CHUNK_SIZE 32768
#define TCG_MAX_TEMPS 512
+#define TCG_MAX_INSNS 512
/* when the size of the arguments of a called function is smaller than
this value, they are statically allocated in the TB stack frame */
--
2.1.0
- Re: [Qemu-devel] [PATCH v2 04/22] target-*: Introduce and use cpu_breakpoint_test, (continued)
- [Qemu-devel] [PATCH v2 09/22] target-s390x: Add cc_op state to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 10/22] target-sh4: Add flags state to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 11/22] target-cris: Mirror gen_opc_pc into insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 12/22] target-sparc: Tidy gen_branch_a interface, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 15/22] target-sparc: Add npc state to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 14/22] target-sparc: Remove gen_opc_jump_pc, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 16/22] tcg: Merge cpu_gen_code into tb_gen_code, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 13/22] target-sparc: Split out gen_branch_n, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 17/22] target-*: Drop cpu_gen_code define, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 18/22] tcg: Add TCG_MAX_INSNS,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 19/22] tcg: Pass data argument to restore_state_to_opc, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 20/22] tcg: Save insn data and use it in cpu_restore_state_from_tb, Richard Henderson, 2015/09/18
- Re: [Qemu-devel] [PATCH v2 20/22] tcg: Save insn data and use it in cpu_restore_state_from_tb, Richard Henderson, 2015/09/19
- Re: [Qemu-devel] [PATCH v2 20/22] tcg: Save insn data and use it in cpu_restore_state_from_tb, Peter Maydell, 2015/09/19
[Qemu-devel] [PATCH v2 22/22] tcg: Remove tcg_gen_code_search_pc, Richard Henderson, 2015/09/18
[Qemu-devel] [PATCH v2 21/22] tcg: Remove gen_intermediate_code_pc, Richard Henderson, 2015/09/18