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[Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing QEMU to hang |
Date: |
Fri, 18 Sep 2015 12:25:32 +0100 |
cpu_mips_get_random() function is used to generate a random index from
CP0.Wired to TLBSize-1 range. Current implementation avoids generating
the same as before value, hence the while loop. If the guest sets
CP0.Wired to TLBSize-1 (which actually does not sound to be very
practical) QEMU will get stuck in the loop infinitely as we always
generate the same index.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
---
hw/mips/cputimer.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
index 1603600..ba9264b 100644
--- a/hw/mips/cputimer.c
+++ b/hw/mips/cputimer.c
@@ -33,13 +33,18 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
static uint32_t seed = 1;
static uint32_t prev_idx = 0;
uint32_t idx;
+ uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
+
+ if (nb_rand_tlb == 1) {
+ return env->tlb->nb_tlb - 1;
+ }
+
/* Don't return same value twice, so get another value */
do {
/* Use a simple algorithm of Linear Congruential Generator
* from ISO/IEC 9899 standard. */
seed = 1103515245 * seed + 12345;
- idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) +
- env->CP0_Wired;
+ idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
} while (idx == prev_idx);
prev_idx = idx;
return idx;
--
2.1.0
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 03/10] target-mips: Fix RDHWR on CP0.Count, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 05/10] target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing QEMU to hang,
Leon Alrae <=
- [Qemu-devel] [PULL 08/10] target-mips: add missing restriction in DAUI instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 10/10] target-mips: improve exception handling, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random index of TLBWR instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 01/10] target-mips: Use tcg_gen_extrh_i64_i32, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 04/10] target-mips: get rid of MIPS_DEBUG, Leon Alrae, 2015/09/18
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2015/09/18