Re: [Qemu-devel] [PATCH] target-arm: Add MDCR_EL2

[Alex Bennée]

Sergey Fedorov <address@hidden> writes:

> Signed-off-by: Sergey Fedorov <address@hidden>
> ---
>
> This patch is a prerequisite for a debug exception routing patch:
> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03542.html
>
>  target-arm/cpu-qom.h |  1 +
>  target-arm/cpu.c     |  1 +
>  target-arm/cpu.h     |  1 +
>  target-arm/cpu64.c   |  1 +
>  target-arm/helper.c  | 13 +++++++++++++
>  5 files changed, 17 insertions(+)
>
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index 25fb1ce..d2b0769 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -167,6 +167,7 @@ typedef struct ARMCPU {
>      uint64_t id_aa64mmfr0;
>      uint64_t id_aa64mmfr1;
>      uint32_t dbgdidr;
> +    uint32_t mdcr;
>      uint32_t clidr;
>      uint64_t mp_affinity; /* MP ID without feature bits */
>      /* The elements of this array are the CCSIDR values for each cache,
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index d7b4445..6474c0d 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -1125,6 +1125,7 @@ static void cortex_a15_initfn(Object *obj)
>      cpu->id_isar3 = 0x11112131;
>      cpu->id_isar4 = 0x10011142;
>      cpu->dbgdidr = 0x3515f021;
> +    cpu->mdcr = 0x00000006;
>      cpu->clidr = 0x0a200023;
>      cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
>      cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 1b80516..d57ed20 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -380,6 +380,7 @@ typedef struct CPUARMState {
>          uint64_t dbgwvr[16]; /* watchpoint value registers */
>          uint64_t dbgwcr[16]; /* watchpoint control registers */
>          uint64_t mdscr_el1;
> +        uint64_t mdcr_el2;

Given we already have banked el3 regs shouldn't this be:

           uint64_6 mdcr_el[4]

?
>          /* If the counter is enabled, this stores the last time the counter
>           * was reset. Otherwise it stores the counter value
>           */
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 63c8b1c..a41cd28 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -136,6 +136,7 @@ static void aarch64_a57_initfn(Object *obj)
>      cpu->id_aa64isar0 = 0x00011120;
>      cpu->id_aa64mmfr0 = 0x00001124;
>      cpu->dbgdidr = 0x3516d000;
> +    cpu->mdcr = 0x00000006;
>      cpu->clidr = 0x0a200023;
>      cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
>      cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 12ea88f..5fe1291 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3221,6 +3221,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>      { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> @@ -3870,6 +3873,13 @@ static void define_debug_regs(ARMCPU *cpu)
>          .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 
> 0,
>          .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
>      };
> +    ARMCPRegInfo mdcr_el2 = {
> +        .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
> +        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
> +        .access = PL2_RW,
> +        .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
> +        .resetvalue = cpu->mdcr,
> +    };
>  
>      /* Note that all these register fields hold "number of Xs minus 1". */
>      brps = extract32(cpu->dbgdidr, 24, 4);
> @@ -3894,6 +3904,9 @@ static void define_debug_regs(ARMCPU *cpu)
>      if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
>          define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
>      }
> +    if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
> +        define_one_arm_cp_reg(cpu, &mdcr_el2);
> +    }
>  
>      for (i = 0; i < brps + 1; i++) {
>          ARMCPRegInfo dbgregs[] = {

-- 
Alex Bennée