Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

[Richard Henderson]

On 10/01/2015 10:37 PM, address@hidden wrote:
>           {
>            mtspr INTERRUPT_CRITICAL_SECTION, r3
>            shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
>           }
>
>           {
>            mtspr EX_CONTEXT_0_0, lr
>            ori r2, r2, RETURN_PL
>           }
>
>           {
>            or r0, r1, r0
>            mtspr EX_CONTEXT_0_1, r2
>           }
>
>           iret
>
>           jrp lr
>
> Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so
> just skip them, at present. "jrp lr" in __longjmp is for historical
> reasons, and might get removed in the future.

So, really, iret is supposed to branch to EX_CONTEXT_0_0, and (presumably) 
validate the privilege level in EX_CONTEXT_0_1 continues to be user-mode.

> +    case OE_RR_X1(IRET):
> +        if (srca) {
> +            return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +        }
> +        srca = TILEGX_R_LR;
> +        mnemonic = "iret";
> +        goto do_jr;

which means this is wrong, but just happens to work for __longjmp.

It appears that the entire point of this iret path is to atomically branch and 
set INTERRUPT_CRITICAL_SECTION at the same time.  So, this isn't complete.

What INTERRUPT_CRITICAL_SECTION is supposed to *do* at user mode, I don't know.


r~