It disables interrupts from being delivered. This means asynchronous
interrupts get deferred until ICS is set back to zero, and synchronous
interrupts (page fault, etc) cause a double-fault instead. ICS is automatically
set on entry to interrupt handlers, so the handler has time to acquire any
information about the interrupt from SPRs, and it is expected that ICS is
cleared as soon as possible. ICS can also be used before returning from
interrupts if you need to do something like adjust the interrupt mask prior to
returning.
In general we want to avoid ever touching memory while within an
interrupt critical section, since the page fault path goes through
a different path from the hypervisor when in an interrupt critical
section, and we carefully decided with tilegx that we didn't need
to support this path in the kernel.