Re: [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5

[Edgar E. Iglesias]

On Thu, Oct 01, 2015 at 05:49:20PM -0700, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <address@hidden>
> 
> Hi,
> 
> Another round of patches towards EL2 support. This one adds partial
> support for 2-stage MMU for AArch64. I've marked it RFC because I
> expect a few iterations. Once we can settle on the approach I'll
> add the AArch32 support (changes for arm_ldl_ptw etc). I've probably
> missed alot of details aswell.
> 
> Some of the details of error reporting are intentionally missing, I
> was thinking to add those incrementally as they get quite involved
> (e.g the register target and memory access size).
> 
> Some of the patches at the start of the series might be good already,
> please pick them up if you agree Peter!
> 
> Comments welcome!


Please ignore this v2, I'll be sending a v3 shortly...

Cheers,
Edgar


> 
> Best regards,
> Edgar
> 
> v1 -> v2:
> * Fix HPFAR_EL2 access checks
> * Prettify computation of starting level for S2 PTW
> * Improve description of ap argument to get_S2prot
> * Fix EXEC protection in get_S2prot
> * Improve comments on S2 PTW attribute extraction
> 
> Edgar E. Iglesias (8):
>   target-arm: Add HPFAR_EL2
>   target-arm: Add computation of starting level for S2 PTW
>   target-arm: Add support for S2 page-table protection bits
>   target-arm: Avoid inline for get_phys_addr
>   target-arm: Add ARMMMUFaultInfo
>   target-arm: Add S2 translation support for S1 PTW
>   target-arm: Route S2 MMU faults to EL2
>   target-arm: Add support for S1 + S2 MMU translations
> 
>  target-arm/cpu.h       |   1 +
>  target-arm/helper.c    | 216 
> ++++++++++++++++++++++++++++++++++++++++---------
>  target-arm/internals.h |  11 ++-
>  target-arm/op_helper.c |  17 ++--
>  4 files changed, 200 insertions(+), 45 deletions(-)
> 
> -- 
> 1.9.1
>