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Re: [Qemu-devel] [PATCH] target-mips: Add SIGRIE instruction
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From: |
Leon Alrae |
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Subject: |
Re: [Qemu-devel] [PATCH] target-mips: Add SIGRIE instruction |
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Date: |
Tue, 6 Oct 2015 14:38:52 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 |
On 05/10/15 10:33, Yongbok Kim wrote:
> @@ -18958,6 +18964,10 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> gen_trap(ctx, op1, rs, -1, imm);
> break;
> + case OPC_SIGRIE:
> + check_insn(ctx, ISA_MIPS32R6);
> + generate_exception_err(ctx, EXCP_RI, extract32(ctx->opcode, 0,
> 16));
Code field is passed as the error_code, but it isn't used later anywhere
and just causes confusion. MIPS BIS document doesn't require any
specific behaviour related to this field, thus in QEMU we should ignore
it and just call generate_exception_end(ctx, EXCP_RI) here.
Leon